Decoupled critical path report generation from its printing
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
12adbb81b1
commit
d8571b6c00
402
common/timing.cc
402
common/timing.cc
@ -640,6 +640,30 @@ struct CriticalPath
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typedef dict<ClockPair, CriticalPath> CriticalPathMap;
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struct CriticalPathSegment
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{
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enum class Type {
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LOGIC,
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ROUTING
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};
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std::pair<CellInfo*,IdString> from;
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std::pair<CellInfo*,IdString> to;
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Type type;
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const NetInfo* net;
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delay_t delay;
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delay_t budget;
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};
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typedef std::vector<CriticalPathSegment> CriticalPathSegments;
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struct CriticalPathReport
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{
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ClockPair clock_pair;
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CriticalPathSegments segments;
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delay_t period;
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};
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typedef dict<ClockPair, CriticalPathReport> CriticalPathReportMap;
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struct NetSinkTiming
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{
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ClockPair clock_pair;
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@ -1141,9 +1165,101 @@ void assign_budget(Context *ctx, bool quiet)
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void write_timing_report(
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Context* ctx,
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const std::string& file_name,
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const std::map<IdString, CriticalPathReport> clock_reports,
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const std::vector<CriticalPathReport> xclock_reports,
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const DetailedNetTimings& detailed_net_timings
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);
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CriticalPathReport build_critical_path_report(Context* ctx, ClockPair &clocks, const PortRefVector &crit_path) {
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CriticalPathReport report;
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report.clock_pair = clocks;
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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int port_clocks;
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auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
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const CellInfo* last_cell = front->cell;
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IdString last_port = front_driver.port;
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int clock_start = -1;
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if (portClass == TMG_REGISTER_OUTPUT) {
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for (int i = 0; i < port_clocks; i++) {
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TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
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const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
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if (clknet != nullptr && clknet->name == clocks.start.clock &&
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clockInfo.edge == clocks.start.edge) {
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last_port = clockInfo.clock_port;
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clock_start = i;
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break;
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}
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}
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}
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayQuad comb_delay;
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if (clock_start != -1) {
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auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
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comb_delay = clockInfo.clockToQ;
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clock_start = -1;
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} else if (last_port == driver.port) {
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// Case where we start with a STARTPOINT etc
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comb_delay = DelayQuad(0);
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} else {
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ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
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}
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CriticalPathSegment seg_logic;
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seg_logic.type = CriticalPathSegment::Type::LOGIC;
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seg_logic.delay = comb_delay.maxDelay();
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seg_logic.budget = 0;
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seg_logic.from = std::make_pair(const_cast<CellInfo*>(last_cell), last_port);
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seg_logic.to = std::make_pair(driver_cell, driver.port);
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seg_logic.net = nullptr;
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report.segments.push_back(seg_logic);
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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CriticalPathSegment seg_route;
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seg_route.type = CriticalPathSegment::Type::ROUTING;
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seg_route.delay = net_delay;
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seg_route.budget = sink->budget;
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seg_route.from = std::make_pair(driver_cell, driver.port);
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seg_route.to = std::make_pair(sink_cell, sink->port);
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seg_route.net = net;
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report.segments.push_back(seg_route);
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last_cell = sink_cell;
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last_port = sink->port;
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}
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int clockCount = 0;
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auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
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if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
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auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
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delay_t setup = sinkClockInfo.setup.maxDelay();
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CriticalPathSegment seg_logic;
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seg_logic.type = CriticalPathSegment::Type::LOGIC;
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seg_logic.delay = setup;
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seg_logic.budget = 0;
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seg_logic.from = std::make_pair(nullptr, IdString());
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seg_logic.to = std::make_pair(const_cast<CellInfo*>(last_cell), last_port);
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seg_logic.net = nullptr;
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report.segments.push_back(seg_logic);
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}
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return report;
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}
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void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool print_path, bool warn_on_failure, bool write_report)
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{
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auto format_event = [ctx](const ClockEvent &e, int field_width = 0) {
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@ -1164,11 +1280,17 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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Timing timing(ctx, true /* net_delays */, false /* update */, (print_path || print_fmax) ? &crit_paths : nullptr,
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print_histogram ? &slack_histogram : nullptr, write_report ? &detailed_net_timings : nullptr);
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timing.walk_paths();
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std::map<IdString, std::pair<ClockPair, CriticalPath>> clock_reports;
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bool report_critical_paths = print_path || print_fmax || write_report;
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std::map<IdString, CriticalPathReport> clock_reports;
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std::vector<CriticalPathReport> xclock_reports;
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std::map<IdString, double> clock_fmax;
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std::vector<ClockPair> xclock_paths;
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std::set<IdString> empty_clocks; // set of clocks with no interior paths
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if (print_path || print_fmax) {
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if (report_critical_paths) {
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for (auto path : crit_paths) {
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const ClockEvent &a = path.first.start;
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const ClockEvent &b = path.first.end;
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@ -1187,8 +1309,9 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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else
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Fmax = 500 / ctx->getDelayNS(path.second.path_delay);
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if (!clock_fmax.count(a.clock) || Fmax < clock_fmax.at(a.clock)) {
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clock_reports[a.clock] = path;
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clock_fmax[a.clock] = Fmax;
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clock_reports[a.clock] = build_critical_path_report(ctx, path.first, path.second.ports);
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clock_reports[a.clock].period = path.second.path_period;
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}
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}
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@ -1197,14 +1320,21 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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const ClockEvent &b = path.first.end;
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if (a.clock == b.clock && a.clock != ctx->id("$async$"))
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continue;
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xclock_paths.push_back(path.first);
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auto &crit_path = crit_paths.at(path.first).ports;
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xclock_reports.push_back(build_critical_path_report(ctx, path.first, crit_path));
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xclock_reports.back().period = path.second.path_period;
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}
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if (clock_reports.empty()) {
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log_info("No Fmax available; no interior timing paths found in design.\n");
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}
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std::sort(xclock_paths.begin(), xclock_paths.end(), [ctx](const ClockPair &a, const ClockPair &b) {
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std::sort(xclock_reports.begin(), xclock_reports.end(), [ctx](const CriticalPathReport &ra, const CriticalPathReport &rb) {
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const auto& a = ra.clock_pair;
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const auto& b = rb.clock_pair;
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if (a.start.clock.str(ctx) < b.start.clock.str(ctx))
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return true;
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if (a.start.clock.str(ctx) > b.start.clock.str(ctx))
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@ -1223,124 +1353,86 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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});
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}
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// Print critical paths
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if (print_path) {
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static auto print_net_source = [](Context *ctx, NetInfo *net) {
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// Check if this net is annotated with a source list
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auto sources = net->attrs.find(ctx->id("src"));
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if (sources == net->attrs.end()) {
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// No sources for this net, can't print anything
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return;
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}
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// Sources are separated by pipe characters.
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// There is no guaranteed ordering on sources, so we just print all
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auto sourcelist = sources->second.as_string();
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std::vector<std::string> source_entries;
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size_t current = 0, prev = 0;
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while ((current = sourcelist.find("|", prev)) != std::string::npos) {
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source_entries.emplace_back(sourcelist.substr(prev, current - prev));
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prev = current + 1;
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}
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// Ensure we emplace the final entry
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source_entries.emplace_back(sourcelist.substr(prev, current - prev));
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// Iterate and print our source list at the correct indentation level
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log_info(" Defined in:\n");
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for (auto entry : source_entries) {
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log_info(" %s\n", entry.c_str());
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}
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};
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auto print_path_report = [ctx](ClockPair &clocks, PortRefVector &crit_path) {
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auto print_path_report = [ctx](const CriticalPathReport& report) {
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delay_t total = 0, logic_total = 0, route_total = 0;
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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int port_clocks;
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auto portClass = ctx->getPortTimingClass(front_driver.cell, front_driver.port, port_clocks);
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IdString last_port = front_driver.port;
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int clock_start = -1;
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if (portClass == TMG_REGISTER_OUTPUT) {
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for (int i = 0; i < port_clocks; i++) {
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TimingClockingInfo clockInfo = ctx->getPortClockingInfo(front_driver.cell, front_driver.port, i);
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const NetInfo *clknet = get_net_or_empty(front_driver.cell, clockInfo.clock_port);
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if (clknet != nullptr && clknet->name == clocks.start.clock &&
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clockInfo.edge == clocks.start.edge) {
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last_port = clockInfo.clock_port;
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clock_start = i;
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break;
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}
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}
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}
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log_info("curr total\n");
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayQuad comb_delay;
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if (clock_start != -1) {
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auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
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comb_delay = clockInfo.clockToQ;
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clock_start = -1;
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} else if (last_port == driver.port) {
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// Case where we start with a STARTPOINT etc
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comb_delay = DelayQuad(0);
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} else {
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ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
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}
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total += comb_delay.maxDelay();
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logic_total += comb_delay.maxDelay();
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log_info("%4.1f %4.1f Source %s.%s\n", ctx->getDelayNS(comb_delay.maxDelay()), ctx->getDelayNS(total),
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driver_cell->name.c_str(ctx), driver.port.c_str(ctx));
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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total += net_delay;
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route_total += net_delay;
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auto driver_loc = ctx->getBelLocation(driver_cell->bel);
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auto sink_loc = ctx->getBelLocation(sink_cell->bel);
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log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(net_delay),
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ctx->getDelayNS(total), net->name.c_str(ctx), ctx->getDelayNS(sink->budget), driver_loc.x,
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driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
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if (ctx->verbose) {
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auto driver_wire = ctx->getNetinfoSourceWire(net);
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auto sink_wire = ctx->getNetinfoSinkWire(net, *sink, 0);
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log_info(" prediction: %f ns estimate: %f ns\n",
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ctx->getDelayNS(ctx->predictDelay(net, *sink)),
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ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
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auto cursor = sink_wire;
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delay_t delay;
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while (driver_wire != cursor) {
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#ifdef ARCH_ECP5
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if (net->is_global)
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break;
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#endif
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auto it = net->wires.find(cursor);
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assert(it != net->wires.end());
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auto pip = it->second.pip;
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NPNR_ASSERT(pip != PipId());
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delay = ctx->getPipDelay(pip).maxDelay();
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log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
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cursor = ctx->getPipSrcWire(pip);
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for (const auto& segment : report.segments) {
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total += segment.delay;
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if (segment.type == CriticalPathSegment::Type::LOGIC) {
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logic_total += segment.delay;
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if (segment.from.first != nullptr) {
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log_info("%4.1f %4.1f Source %s.%s\n",
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ctx->getDelayNS(segment.delay),
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ctx->getDelayNS(total),
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segment.from.first->name.c_str(ctx),
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segment.from.second.c_str(ctx)
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);
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}
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else {
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log_info("%4.1f %4.1f Setup %s.%s\n",
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ctx->getDelayNS(segment.delay),
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ctx->getDelayNS(total),
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segment.to.first->name.c_str(ctx),
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segment.to.second.c_str(ctx)
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);
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}
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}
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if (!ctx->disable_critical_path_source_print) {
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print_net_source(ctx, net);
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if (segment.type == CriticalPathSegment::Type::ROUTING) {
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route_total += segment.delay;
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auto driver_loc = ctx->getBelLocation(segment.from.first->bel);
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auto sink_loc = ctx->getBelLocation(segment.to.first->bel);
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log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n",
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ctx->getDelayNS(segment.delay),
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ctx->getDelayNS(total),
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segment.net->name.c_str(ctx),
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ctx->getDelayNS(segment.budget),
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driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y
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);
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log_info(" Sink %s.%s\n",
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segment.to.first->name.c_str(ctx),
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segment.to.second.c_str(ctx)
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);
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if (ctx->verbose) {
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PortRef sink;
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sink.cell = segment.to.first;
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sink.port = segment.to.second;
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sink.budget = segment.budget;
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auto net = segment.net;
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auto driver_wire = ctx->getNetinfoSourceWire(net);
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auto sink_wire = ctx->getNetinfoSinkWire(net, sink, 0);
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log_info(" prediction: %f ns estimate: %f ns\n",
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ctx->getDelayNS(ctx->predictDelay(net, sink)),
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ctx->getDelayNS(ctx->estimateDelay(driver_wire, sink_wire)));
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auto cursor = sink_wire;
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delay_t delay;
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while (driver_wire != cursor) {
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#ifdef ARCH_ECP5
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if (net->is_global)
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break;
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#endif
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auto it = net->wires.find(cursor);
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assert(it != net->wires.end());
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auto pip = it->second.pip;
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NPNR_ASSERT(pip != PipId());
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delay = ctx->getPipDelay(pip).maxDelay();
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log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
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cursor = ctx->getPipSrcWire(pip);
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}
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}
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}
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last_port = sink->port;
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}
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int clockCount = 0;
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auto sinkClass = ctx->getPortTimingClass(crit_path.back()->cell, crit_path.back()->port, clockCount);
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if (sinkClass == TMG_REGISTER_INPUT && clockCount > 0) {
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auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
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delay_t setup = sinkClockInfo.setup.maxDelay();
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total += setup;
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logic_total += setup;
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log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total),
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crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx));
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}
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log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
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};
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@ -1348,24 +1440,24 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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for (auto &clock : clock_reports) {
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log_break();
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std::string start =
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clock.second.first.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
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clock.second.clock_pair.start.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
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std::string end =
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clock.second.first.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
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clock.second.clock_pair.end.edge == FALLING_EDGE ? std::string("negedge") : std::string("posedge");
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log_info("Critical path report for clock '%s' (%s -> %s):\n", clock.first.c_str(ctx), start.c_str(),
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end.c_str());
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auto &crit_path = clock.second.second.ports;
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print_path_report(clock.second.first, crit_path);
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auto &report = clock.second;
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print_path_report(report);
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}
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for (auto &xclock : xclock_paths) {
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for (auto &report : xclock_reports) {
|
||||
log_break();
|
||||
std::string start = format_event(xclock.start);
|
||||
std::string end = format_event(xclock.end);
|
||||
std::string start = format_event(report.clock_pair.start);
|
||||
std::string end = format_event(report.clock_pair.end);
|
||||
log_info("Critical path report for cross-domain path '%s' -> '%s':\n", start.c_str(), end.c_str());
|
||||
auto &crit_path = crit_paths.at(xclock).ports;
|
||||
print_path_report(xclock, crit_path);
|
||||
print_path_report(report);
|
||||
}
|
||||
}
|
||||
|
||||
if (print_fmax) {
|
||||
log_break();
|
||||
unsigned max_width = 0;
|
||||
@ -1401,17 +1493,20 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
log_break();
|
||||
|
||||
int start_field_width = 0, end_field_width = 0;
|
||||
for (auto &xclock : xclock_paths) {
|
||||
start_field_width = std::max((int)format_event(xclock.start).length(), start_field_width);
|
||||
end_field_width = std::max((int)format_event(xclock.end).length(), end_field_width);
|
||||
for (auto &report : xclock_reports) {
|
||||
start_field_width = std::max((int)format_event(report.clock_pair.start).length(), start_field_width);
|
||||
end_field_width = std::max((int)format_event(report.clock_pair.end).length(), end_field_width);
|
||||
}
|
||||
|
||||
for (auto &xclock : xclock_paths) {
|
||||
const ClockEvent &a = xclock.start;
|
||||
const ClockEvent &b = xclock.end;
|
||||
auto &path = crit_paths.at(xclock);
|
||||
for (auto &report : xclock_reports) {
|
||||
const ClockEvent &a = report.clock_pair.start;
|
||||
const ClockEvent &b = report.clock_pair.end;
|
||||
delay_t path_delay = 0;
|
||||
for (const auto& segment : report.segments) {
|
||||
path_delay += segment.delay;
|
||||
}
|
||||
auto ev_a = format_event(a, start_field_width), ev_b = format_event(b, end_field_width);
|
||||
log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path.path_delay));
|
||||
log_info("Max delay %s -> %s: %0.02f ns\n", ev_a.c_str(), ev_b.c_str(), ctx->getDelayNS(path_delay));
|
||||
}
|
||||
log_break();
|
||||
}
|
||||
@ -1455,14 +1550,20 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
|
||||
}
|
||||
|
||||
if (!report_file.empty()) {
|
||||
log_info("\nWriting timing analysis report...\n");
|
||||
write_timing_report(ctx, report_file, detailed_net_timings);
|
||||
log_break();
|
||||
log_info("Writing timing analysis report...\n");
|
||||
write_timing_report(ctx, report_file,
|
||||
clock_reports,
|
||||
xclock_reports,
|
||||
detailed_net_timings);
|
||||
}
|
||||
}
|
||||
|
||||
void write_timing_report(
|
||||
Context* ctx,
|
||||
const std::string& file_name,
|
||||
const std::map<IdString, CriticalPathReport> clock_reports,
|
||||
const std::vector<CriticalPathReport> xclock_reports,
|
||||
const DetailedNetTimings& detailed_net_timings
|
||||
)
|
||||
{
|
||||
@ -1486,11 +1587,39 @@ void write_timing_report(
|
||||
return value;
|
||||
};
|
||||
|
||||
// auto report_critical_path = [ctx](const ClockPair &clocks, const PortRefVector &path) {
|
||||
// }
|
||||
|
||||
// Open the file
|
||||
FILE* fp = fopen(file_name.c_str(), "w");
|
||||
NPNR_ASSERT(fp != nullptr);
|
||||
|
||||
// Detailed net timing analysis
|
||||
// Critical paths
|
||||
auto critPathsJson = Json::array();
|
||||
for (auto &report : clock_reports) {
|
||||
|
||||
critPathsJson.push_back(Json::object({
|
||||
{"from", event_name(report.second.clock_pair.start)},
|
||||
{"to", event_name(report.second.clock_pair.end)},
|
||||
{"path", Json()}
|
||||
}));
|
||||
|
||||
//auto &crit_path = clock.second.second.ports;
|
||||
//print_path_report(clock.second.first, crit_path);
|
||||
}
|
||||
|
||||
// Cross-domain paths
|
||||
for (auto &report : xclock_reports) {
|
||||
critPathsJson.push_back(Json::object({
|
||||
{"from", event_name(report.clock_pair.start)},
|
||||
{"to", event_name(report.clock_pair.end)},
|
||||
{"path", Json()}
|
||||
}));
|
||||
// auto &crit_path = crit_paths.at(xclock).ports;
|
||||
// print_path_report(xclock, crit_path);
|
||||
}
|
||||
|
||||
// Detailed per-net timing analysis
|
||||
auto detailedNetTimingsJson = Json::array();
|
||||
for (const auto& it : detailed_net_timings) {
|
||||
const NetInfo* net = it.first;
|
||||
@ -1524,6 +1653,7 @@ void write_timing_report(
|
||||
}
|
||||
|
||||
auto analysisJson = Json::object({
|
||||
{"critical_paths", Json(critPathsJson)},
|
||||
{"detailed_net_timings", Json(detailedNetTimingsJson)}
|
||||
});
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user