timing: Update to new use API (currently broken)
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -84,20 +84,20 @@ struct Timing
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input_ports.push_back(port.first);
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}
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bool is_io = ctx->isIOCell(cell.second.get());
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for (auto o : output_ports) {
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IdString clock_domain = ctx->getPortClock(cell.second.get(), o->name);
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clockPort);
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// If output port is influenced by a clock (e.g. FF output)
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// then add it to the ordering as a timing start-point
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if (clock_domain != IdString()) {
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if (portClass == TMG_REGISTER_OUTPUT) {
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DelayInfo clkToQ;
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ctx->getCellDelay(cell.second.get(), clock_domain, o->name, clkToQ);
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ctx->getCellDelay(cell.second.get(), clockPort, o->name, clkToQ);
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topographical_order.emplace_back(o->net);
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net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
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} else {
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// Also add I/O cells too
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// TODO(eddieh): More generic way of detecting PLLs
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if (is_io || cell.second->type == ctx->id("ICESTORM_PLL")) {
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if (portClass == TMG_STARTPOINT || portClass == TMG_IGNORE) { // IGNORE: ????
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topographical_order.emplace_back(o->net);
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net_data.emplace(o->net, TimingData{});
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}
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@ -137,12 +137,13 @@ struct Timing
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DelayInfo clkToQ;
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for (auto &usr : net->users) {
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auto clock_domain = ctx->getPortClock(usr.cell, usr.port);
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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for (auto &port : usr.cell->ports) {
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if (port.second.type != PORT_OUT || !port.second.net)
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continue;
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// Skip if this is a clocked output (but allow non-clocked ones)
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if (clock_domain != IdString() && ctx->getCellDelay(usr.cell, clock_domain, port.first, clkToQ))
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if (portClass == TMG_REGISTER_OUTPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE)
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continue;
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DelayInfo comb_delay;
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bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
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@ -173,7 +174,9 @@ struct Timing
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const auto net_length_plus_one = nd.max_path_length + 1;
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nd.min_remaining_budget = clk_period;
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for (auto &usr : net->users) {
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if (ctx->getPortClock(usr.cell, usr.port) != IdString()) {
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IdString clockPort;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, clockPort);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT || portClass == TMG_IGNORE) {
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} else {
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auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
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auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
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@ -212,7 +215,9 @@ struct Timing
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for (auto &usr : net->users) {
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auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
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auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
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if (ctx->getPortClock(usr.cell, usr.port) != IdString()) {
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IdString associatedClock;
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TimingPortClass portClass = ctx->getPortTimingClass(usr.cell, usr.port, associatedClock);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_ENDPOINT) {
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const auto net_arrival = nd.max_arrival;
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auto path_budget = clk_period - (net_arrival + net_delay);
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if (update) {
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@ -267,7 +272,10 @@ struct Timing
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if (!is_path)
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continue;
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// If input port is influenced by a clock, skip
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if (ctx->getPortClock(crit_net->driver.cell, port.first) != IdString())
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IdString portClock;
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TimingPortClass portClass = ctx->getPortTimingClass(crit_net->driver.cell, port.first, portClock);
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if (portClass == TMG_REGISTER_INPUT || portClass == TMG_CLOCK_INPUT || portClass == TMG_ENDPOINT ||
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portClass == TMG_IGNORE)
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continue;
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// And find the fanin net with the latest arrival time
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@ -373,7 +381,9 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_path)
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
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IdString last_port;
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ctx->getPortTimingClass(front_driver.cell, front_driver.port, last_port);
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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@ -29,7 +29,8 @@ static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
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NEXTPNR_NAMESPACE_BEGIN
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MainWindow::MainWindow(std::unique_ptr<Context> context, ArchArgs args, QWidget *parent) : BaseMainWindow(std::move(context), args, parent)
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MainWindow::MainWindow(std::unique_ptr<Context> context, ArchArgs args, QWidget *parent)
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: BaseMainWindow(std::move(context), args, parent)
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{
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initMainResource();
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@ -50,7 +51,8 @@ void MainWindow::newContext(Context *ctx)
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setWindowTitle(title.c_str());
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}
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void MainWindow::createMenu() {
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void MainWindow::createMenu()
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{
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// Add arch specific actions
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actionLoadBase = new QAction("Open Base Config", this);
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actionLoadBase->setIcon(QIcon(":/icons/resources/open_base.png"));
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@ -71,7 +73,7 @@ void MainWindow::createMenu() {
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menuDesign->addSeparator();
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menuDesign->addAction(actionLoadBase);
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menuDesign->addAction(actionSaveConfig);
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menuDesign->addAction(actionSaveConfig);
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}
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static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
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@ -96,8 +98,8 @@ static QStringList getSupportedPackages(ArchArgs::ArchArgsTypes chip)
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return packages;
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}
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void MainWindow::new_proj() {
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void MainWindow::new_proj()
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{
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QMap<QString, int> arch;
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arch.insert("Lattice ECP5 25K", ArchArgs::LFE5U_25F);
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arch.insert("Lattice ECP5 45K", ArchArgs::LFE5U_45F);
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@ -47,6 +47,7 @@ class MainWindow : public BaseMainWindow
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void newContext(Context *ctx);
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void open_base();
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void save_config();
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private:
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QAction *actionLoadBase;
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QAction *actionSaveConfig;
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@ -23,7 +23,8 @@ static void initMainResource() { Q_INIT_RESOURCE(nextpnr); }
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NEXTPNR_NAMESPACE_BEGIN
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MainWindow::MainWindow(std::unique_ptr<Context> context, ArchArgs args, QWidget *parent) : BaseMainWindow(std::move(context), args, parent)
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MainWindow::MainWindow(std::unique_ptr<Context> context, ArchArgs args, QWidget *parent)
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: BaseMainWindow(std::move(context), args, parent)
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{
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initMainResource();
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@ -915,7 +915,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
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}
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} else if (cell->type == id_icestorm_ram || cell->type == id("ICESTORM_DSP") ||
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cell->type == id("ICESTORM_SPRAM")) {
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if (port == id_clk)
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if (port == id_clk || port == id_rclk || port == id_wclk)
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return TMG_CLOCK_INPUT;
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else if (cell->ports.at(port).type == PORT_OUT)
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return TMG_REGISTER_OUTPUT;
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@ -925,7 +925,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id
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if (port == id("D_IN_0") || port == id("D_IN_1"))
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return TMG_STARTPOINT;
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if (port == id("D_OUT_0") || port == id("D_OUT_1"))
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return TMG_STARTPOINT;
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return TMG_ENDPOINT;
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return TMG_IGNORE;
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} else if (cell->type == id("ICESTORM_PLL")) {
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if (port == id("PLLOUT_A") || port == id("PLLOUT_B"))
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