Merge pull request #586 from litghost/add_cell_bel_mapping_only
Add Cell -> BEL Pin maps to FPGA interchange arch.
This commit is contained in:
gatecat
GitHub
commit
da1ecf0813
@ -36,6 +36,30 @@
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#include "util.h"
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#include "xdc.h"
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NEXTPNR_NAMESPACE_BEGIN
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struct SiteBelPair
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{
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std::string site;
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IdString bel;
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SiteBelPair() {}
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SiteBelPair(std::string site, IdString bel) : site(site), bel(bel) {}
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bool operator==(const SiteBelPair &other) const { return site == other.site && bel == other.bel; }
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};
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NEXTPNR_NAMESPACE_END
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template <> struct std::hash<NEXTPNR_NAMESPACE_PREFIX SiteBelPair>
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{
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std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX SiteBelPair &site_bel) const noexcept
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{
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std::size_t seed = 0;
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boost::hash_combine(seed, std::hash<std::string>()(site_bel.site));
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boost::hash_combine(seed, std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(site_bel.bel));
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return seed;
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}
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};
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NEXTPNR_NAMESPACE_BEGIN
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static std::pair<std::string, std::string> split_identifier_name_dot(const std::string &name)
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@ -65,18 +89,16 @@ Arch::Arch(ArchArgs args) : args(args)
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log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
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}
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// Read strings from constids into IdString database, checking that list
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// is unique and matches expected constid value.
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int id = 1;
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for (const auto &constid : *chip_info->constids) {
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IdString::initialize_add(this, constid.get(), id++);
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}
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tileStatus.resize(chip_info->tiles.size());
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for (int i = 0; i < chip_info->tiles.ssize(); i++) {
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tileStatus[i].boundcells.resize(chip_info->tile_types[chip_info->tiles[i].type].bel_data.size());
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}
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const RelSlice<RelPtr<char>> &constids = *chip_info->constids;
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for (size_t i = 0; i < constids.size(); ++i) {
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IdString::initialize_add(this, constids[i].get(), i + 1);
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}
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// Sanity check cell name ids.
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const CellMapPOD &cell_map = *chip_info->cell_map;
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int32_t first_cell_id = cell_map.cell_names[0];
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@ -87,6 +109,51 @@ Arch::Arch(ArchArgs args) : args(args)
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io_port_types.emplace(this->id("$nextpnr_ibuf"));
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io_port_types.emplace(this->id("$nextpnr_obuf"));
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io_port_types.emplace(this->id("$nextpnr_iobuf"));
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if (!this->args.package.empty()) {
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IdString package = this->id(this->args.package);
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package_index = -1;
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for (size_t i = 0; i < chip_info->packages.size(); ++i) {
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if (IdString(chip_info->packages[i].package) == package) {
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NPNR_ASSERT(package_index == -1);
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package_index = i;
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}
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}
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if (package_index == -1) {
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log_error("Could not find package '%s' in chipdb.\n", this->args.package.c_str());
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}
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} else {
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// Default to first package.
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NPNR_ASSERT(chip_info->packages.size() > 0);
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if(chip_info->packages.size() == 1) {
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IdString package_name(chip_info->packages[0].package);
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this->args.package = package_name.str(this);
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package_index = 0;
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} else {
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log_info("Package must be specified (with --package arg) when multiple packages are available, packages:\n");
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for(const auto &package : chip_info->packages) {
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log_info(" - %s\n", IdString(package.package).c_str(this));
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}
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log_error("--package is required!\n");
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}
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}
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std::unordered_set<SiteBelPair> site_bel_pads;
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for (const auto &package_pin : chip_info->packages[package_index].pins) {
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IdString site(package_pin.site);
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IdString bel(package_pin.bel);
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site_bel_pads.emplace(SiteBelPair(site.str(this), bel));
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}
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for (BelId bel : getBels()) {
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auto &bel_data = bel_info(chip_info, bel);
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const SiteInstInfoPOD &site = chip_info->sites[chip_info->tiles[bel.tile].sites[bel_data.site]];
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auto iter = site_bel_pads.find(SiteBelPair(site.site_name.get(), IdString(bel_data.name)));
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if (iter != site_bel_pads.end()) {
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pads.emplace(bel);
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}
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}
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}
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// -----------------------------------------------------------------------
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@ -608,4 +675,99 @@ const std::vector<std::string> Arch::availablePlacers = {"sa",
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const std::string Arch::defaultRouter = "router2";
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const std::vector<std::string> Arch::availableRouters = {"router1", "router2"};
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void Arch::map_cell_pins(CellInfo *cell, int32_t mapping) const
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{
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cell->cell_mapping = mapping;
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cell->cell_bel_pins.clear();
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const CellBelMapPOD &cell_pin_map = chip_info->cell_map->cell_bel_map[mapping];
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for (const auto &pin_map : cell_pin_map.common_pins) {
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IdString cell_pin(pin_map.cell_pin);
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IdString bel_pin(pin_map.bel_pin);
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if (cell_pin.str(this) == "GND") {
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// FIXME: Tie this pin to the GND net
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continue;
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}
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if (cell_pin.str(this) == "VCC") {
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// FIXME: Tie this pin to the VCC net
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continue;
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}
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cell->cell_bel_pins[cell_pin].push_back(bel_pin);
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}
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for (const auto ¶meter_pin_map : cell_pin_map.parameter_pins) {
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IdString param_key(parameter_pin_map.key);
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std::string param_value = IdString(parameter_pin_map.value).c_str(this);
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auto iter = cell->params.find(param_key);
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if (iter == cell->params.end()) {
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continue;
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}
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if (param_value != iter->second.as_string()) {
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continue;
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}
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for (const auto &pin_map : parameter_pin_map.pins) {
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IdString cell_pin(pin_map.cell_pin);
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IdString bel_pin(pin_map.bel_pin);
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if (cell_pin.str(this) == "GND") {
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// FIXME: Tie this pin to the GND net
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continue;
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}
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if (cell_pin.str(this) == "VCC") {
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// FIXME: Tie this pin to the VCC net
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continue;
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}
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cell->cell_bel_pins[cell_pin].push_back(bel_pin);
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}
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}
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}
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void Arch::map_port_pins(BelId bel, CellInfo *cell) const
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{
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IdStringRange pins = getBelPins(bel);
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NPNR_ASSERT(pins.begin() != pins.end());
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auto b = pins.begin();
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IdString pin = *b;
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++b;
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NPNR_ASSERT(b == pins.end());
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NPNR_ASSERT(cell->ports.size() == 1);
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cell->cell_bel_pins[cell->ports.begin()->first].clear();
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cell->cell_bel_pins[cell->ports.begin()->first].push_back(pin);
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}
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bool Arch::is_net_within_site(const NetInfo &net) const
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{
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if (net.driver.cell == nullptr || net.driver.cell->bel == BelId()) {
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return false;
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}
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BelId driver = net.driver.cell->bel;
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int32_t site = bel_info(chip_info, driver).site;
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NPNR_ASSERT(site >= 0);
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for (const auto &user : net.users) {
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if (user.cell == nullptr || user.cell->bel == BelId()) {
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return false;
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}
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BelId user_bel = user.cell->bel;
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if (user_bel.tile != driver.tile) {
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return false;
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}
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if (bel_info(chip_info, user_bel).site != site) {
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return false;
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}
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}
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return true;
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}
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NEXTPNR_NAMESPACE_END
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@ -67,7 +67,7 @@ NPNR_PACKED_STRUCT(struct BelInfoPOD {
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int16_t category;
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int16_t padding;
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RelPtr<int8_t> valid_cells; // Bool array, length of number_cells.
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RelPtr<int32_t> pin_map; // Index into CellMapPOD::cell_bel_map
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});
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enum BELCategory
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@ -109,6 +109,12 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
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int16_t extra_data;
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});
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NPNR_PACKED_STRUCT(struct ConstraintTagPOD {
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int32_t tag_prefix; // constid
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int32_t default_state; // constid
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RelSlice<int32_t> states; // constid
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});
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NPNR_PACKED_STRUCT(struct TileTypeInfoPOD {
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int32_t name; // Tile type constid
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@ -119,10 +125,13 @@ NPNR_PACKED_STRUCT(struct TileTypeInfoPOD {
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RelSlice<TileWireInfoPOD> wire_data;
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RelSlice<PipInfoPOD> pip_data;
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RelSlice<ConstraintTagPOD> tags;
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});
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NPNR_PACKED_STRUCT(struct SiteInstInfoPOD {
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RelPtr<char> name;
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RelPtr<char> site_name;
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// Which site type is this site instance?
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// constid
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@ -138,7 +147,7 @@ NPNR_PACKED_STRUCT(struct TileInstInfoPOD {
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// This array is root.tile_types[type].number_sites long.
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// Index into root.sites
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RelPtr<int32_t> sites;
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RelSlice<int32_t> sites;
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// Number of tile wires; excluding any site-internal wires
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// which come after general wires and are not stored here
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@ -154,10 +163,46 @@ NPNR_PACKED_STRUCT(struct TileWireRefPOD {
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NPNR_PACKED_STRUCT(struct NodeInfoPOD { RelSlice<TileWireRefPOD> tile_wires; });
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NPNR_PACKED_STRUCT(struct CellBelPinPOD {
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int32_t cell_pin; // constid
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int32_t bel_pin; // constid
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});
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NPNR_PACKED_STRUCT(struct ParameterPinsPOD {
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int32_t key; // constid
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int32_t value; // constid
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RelSlice<CellBelPinPOD> pins;
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});
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NPNR_PACKED_STRUCT(struct CellConstraintPOD {
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int32_t tag; // Tag index
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int32_t constraint_type; // Constraint::ConstraintType
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RelSlice<int32_t> states; // State indicies
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});
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NPNR_PACKED_STRUCT(struct CellBelMapPOD {
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RelSlice<CellBelPinPOD> common_pins;
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RelSlice<ParameterPinsPOD> parameter_pins;
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RelSlice<CellConstraintPOD> constraints;
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});
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NPNR_PACKED_STRUCT(struct CellMapPOD {
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// Cell names supported in this arch.
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RelSlice<int32_t> cell_names; // constids
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RelSlice<int32_t> cell_bel_buckets; // constids
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RelSlice<CellBelMapPOD> cell_bel_map;
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});
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NPNR_PACKED_STRUCT(struct PackagePinPOD {
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int32_t package_pin; // constid
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int32_t site; // constid
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int32_t bel; // constid
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});
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NPNR_PACKED_STRUCT(struct PackagePOD {
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int32_t package; // constid
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RelSlice<PackagePinPOD> pins;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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@ -171,6 +216,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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RelSlice<SiteInstInfoPOD> sites;
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RelSlice<TileInstInfoPOD> tiles;
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RelSlice<NodeInfoPOD> nodes;
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RelSlice<PackagePOD> packages;
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// BEL bucket constids.
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RelSlice<int32_t> bel_buckets;
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@ -667,7 +713,7 @@ struct ArchRanges
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using TileBelsRangeT = BelRange;
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using BelAttrsRangeT = std::vector<std::pair<IdString, std::string>>;
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using BelPinsRangeT = IdStringRange;
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using CellBelPinRangeT = std::array<IdString, 1>;
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using CellBelPinRangeT = const std::vector<IdString> &;
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// Wires
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using AllWiresRangeT = WireRange;
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using DownhillPipRangeT = DownhillPipRange;
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@ -695,6 +741,7 @@ struct Arch : ArchAPI<ArchRanges>
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{
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boost::iostreams::mapped_file_source blob_file;
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const ChipInfoPOD *chip_info;
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int32_t package_index;
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mutable std::unordered_map<IdString, int> tile_by_name;
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mutable std::unordered_map<IdString, std::pair<int, int>> site_by_name;
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@ -768,12 +815,29 @@ struct Arch : ArchAPI<ArchRanges>
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uint32_t getBelChecksum(BelId bel) const override { return bel.index; }
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void map_cell_pins(CellInfo *cell, int32_t mapping) const;
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void map_port_pins(BelId bel, CellInfo *cell) const;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(tileStatus[bel.tile].boundcells[bel.index] == nullptr);
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tileStatus[bel.tile].boundcells[bel.index] = cell;
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const auto &bel_data = bel_info(chip_info, bel);
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NPNR_ASSERT(bel_data.category == BEL_CATEGORY_LOGIC);
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if (io_port_types.count(cell->type) == 0) {
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int32_t mapping = bel_info(chip_info, bel).pin_map[get_cell_type_index(cell->type)];
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NPNR_ASSERT(mapping >= 0);
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if (cell->cell_mapping != mapping) {
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map_cell_pins(cell, mapping);
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}
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} else {
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map_port_pins(bel, cell);
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}
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cell->bel = bel;
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cell->belStrength = strength;
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refreshUiBel(bel);
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@ -870,12 +934,15 @@ struct Arch : ArchAPI<ArchRanges>
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IdStringRange str_range;
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str_range.b.cursor = &ports[0];
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str_range.e.cursor = &ports[num_bel_wires - 1];
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str_range.e.cursor = &ports[num_bel_wires];
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return str_range;
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}
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std::array<IdString, 1> getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override { return {pin}; }
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const std::vector<IdString> &getBelPinsForCellPin(CellInfo *cell_info, IdString pin) const override
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{
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return cell_info->cell_bel_pins.at(pin);
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}
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// -------------------------------------------------
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@ -1260,6 +1327,12 @@ struct Arch : ArchAPI<ArchRanges>
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BelBucketId getBelBucketForCellType(IdString cell_type) const override
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{
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if (io_port_types.count(cell_type)) {
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BelBucketId bucket;
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bucket.name = id("IOPORTS");
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return bucket;
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}
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BelBucketId bucket;
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const CellMapPOD &cell_map = *chip_info->cell_map;
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bucket.name = IdString(cell_map.cell_bel_buckets[get_cell_type_index(cell_type)]);
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@ -1277,7 +1350,11 @@ struct Arch : ArchAPI<ArchRanges>
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bool isValidBelForCellType(IdString cell_type, BelId bel) const override
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{
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return bel_info(chip_info, bel).valid_cells[get_cell_type_index(cell_type)];
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if (io_port_types.count(cell_type)) {
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return pads.count(bel) > 0;
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} else {
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return bel_info(chip_info, bel).pin_map[get_cell_type_index(cell_type)] > 0;
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}
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}
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// Return true whether all Bels at a given location are valid
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@ -1307,6 +1384,28 @@ struct Arch : ArchAPI<ArchRanges>
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void parse_xdc(const std::string &filename);
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std::unordered_set<IdString> io_port_types;
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std::unordered_set<BelId> pads;
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bool is_site_port(PipId pip) const
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{
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const PipInfoPOD &pip_data = pip_info(chip_info, pip);
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if (pip_data.site == -1) {
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return false;
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}
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BelId bel;
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bel.tile = pip.tile;
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bel.index = pip_data.bel;
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const BelInfoPOD &bel_data = bel_info(chip_info, bel);
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return bel_data.category == BEL_CATEGORY_SITE_PORT;
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}
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// Is the driver and all users of this net located within the same site?
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//
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// Returns false if any element of the net is not placed.
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bool is_net_within_site(const NetInfo &net) const;
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};
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NEXTPNR_NAMESPACE_END
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