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mistral: M10K pack fixes

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-12-22 13:54:30 +00:00 committed by Lofty
parent 78474a5dec
commit da65afc83b
2 changed files with 14 additions and 6 deletions
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2
mistral/arch.cc
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@ -410,6 +410,8 @@ void Arch::add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire)
void Arch::assign_default_pinmap(CellInfo *cell) void Arch::assign_default_pinmap(CellInfo *cell)
{ {
if (cell->type == id_MISTRAL_M10K)
return; // M10Ks always have a custom pinmap
for (auto &port : cell->ports) { for (auto &port : cell->ports) {
auto &pinmap = cell->pin_data[port.first].bel_pins; auto &pinmap = cell->pin_data[port.first].bel_pins;
if (!pinmap.empty()) if (!pinmap.empty())

18
mistral/pack.cc
View File

@ -384,13 +384,13 @@ struct MistralPacker
void setup_m10ks() void setup_m10ks()
{ {
for (auto& cell : ctx->cells) { for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get(); CellInfo *ci = cell.second.get();
if (ci->type != id_MISTRAL_M10K) if (ci->type != id_MISTRAL_M10K)
continue; continue;
auto abits = ci->attrs[id_CFG_ABITS].as_int64(); auto abits = ci->params.at(id_CFG_ABITS).as_int64();
auto dbits = ci->attrs[id_CFG_DBITS].as_int64(); auto dbits = ci->params.at(id_CFG_DBITS).as_int64();
NPNR_ASSERT(abits >= 7 && abits <= 13); NPNR_ASSERT(abits >= 7 && abits <= 13);
NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20); NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20);
@ -417,8 +417,10 @@ struct MistralPacker
bit_offset = 1; bit_offset = 1;
} }
for (int bit = bit_offset; bit < abits; bit++) { for (int bit = bit_offset; bit < abits; bit++) {
ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))}; ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {
ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))}; ctx->id(stringf("ADDRA[%d]", bit + addr_offset))};
ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {
ctx->id(stringf("ADDRB[%d]", bit + addr_offset))};
} }
// Data lines // Data lines
@ -449,7 +451,10 @@ struct MistralPacker
} }
for (int bit = 0; bit < dbits; bit++) { for (int bit = 0; bit < dbits; bit++) {
for (int offset : offsets) { for (int offset : offsets) {
ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset))); log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))),
ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset))));
ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
ctx->id(stringf("DATAAIN[%d]", bit + offset)));
} }
} }
@ -466,6 +471,7 @@ struct MistralPacker
pack_io(); pack_io();
constrain_carries(); constrain_carries();
constrain_lutram(); constrain_lutram();
setup_m10ks();
} }
}; };
}; // namespace }; // namespace