Himbaechel xilinx : Add support of DSP packing for 7-series
This commit is contained in:
Adrien Prost-Boucle
myrtle
parent
bbdf7aacb0
commit
db0c99199e
@ -742,7 +742,7 @@ void XilinxImpl::pack()
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packer.pack_luts();
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packer.pack_luts();
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packer.pack_dram();
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packer.pack_dram();
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packer.pack_bram();
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packer.pack_bram();
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// packer.pack_dsps();
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packer.pack_dsps();
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packer.pack_ffs();
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packer.pack_ffs();
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packer.finalise_muxfs();
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packer.finalise_muxfs();
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packer.pack_lutffs();
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packer.pack_lutffs();
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165
himbaechel/uarch/xilinx/pack_dsp_xc7.cc
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165
himbaechel/uarch/xilinx/pack_dsp_xc7.cc
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@ -0,0 +1,165 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2020 Myrtle Shah <gatecat@ds0.me>
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* Copyright (C) 2023 Hans Baier <hansfbaier@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <boost/algorithm/string.hpp>
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#include "pack.h"
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#define HIMBAECHEL_CONSTIDS "uarch/xilinx/constids.inc"
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#include "himbaechel_constids.h"
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NEXTPNR_NAMESPACE_BEGIN
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void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
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{
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CellInfo *cascaded_cell = nullptr;
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auto check_illegal_fanout = [&] (NetInfo *ni, std::string port) {
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if (ni->users.entries() > 1)
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log_error("Port %s connected to net %s has more than one user", port.c_str(), ni->name.c_str(ctx));
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PortRef& user = *ni->users.begin();
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if (user.cell->type != id_DSP48E1_DSP48E1)
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log_error("User %s of net %s is not a DSP block, but %s",
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user.cell->name.c_str(ctx), ni->name.c_str(ctx), user.cell->type.c_str(ctx));
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};
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// see if any cascade outputs are connected
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for (auto port : current_cell->ports) {
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if (!boost::contains(port.first.str(ctx), "COUT")) continue;
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NetInfo *cout_net = port.second.net;
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if (cout_net == nullptr) continue;
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check_illegal_fanout(cout_net, port.first.c_str(ctx));
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PortRef& user = *cout_net->users.begin();
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CellInfo *cout_cell = user.cell;
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NPNR_ASSERT(cout_cell != nullptr);
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if (cascaded_cell != nullptr && cout_cell != cascaded_cell)
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log_error("the cascading outputs of DSP block %s are connected to different cells",
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current_cell->name.c_str(ctx));
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cascaded_cell = cout_cell;
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}
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if (cascaded_cell != nullptr) {
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auto is_lower_bel = constr_z == BEL_LOWER_DSP;
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cascaded_cell->cluster = root->name;
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root->constr_children.push_back(cascaded_cell);
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cascaded_cell->constr_x = 0;
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// the connected cell has to be above the current cell,
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// otherwise it cannot be routed, because the cascading ports
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// are only connected to the DSP above
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auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
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cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
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cascaded_cell->constr_z = constr_z;
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cascaded_cell->constr_abs_z = true;
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walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
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}
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}
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void XC7Packer::pack_dsps()
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{
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log_info("Packing DSPs..\n");
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dict<IdString, XFormRule> dsp_rules;
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dsp_rules[id_DSP48E1].new_type = id_DSP48E1_DSP48E1;
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generic_xform(dsp_rules, true);
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std::vector<CellInfo *> all_dsps;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto add_const_pin = [&](PortInfo& port, std::string& pins, std::string& pin_name, std::string net) {
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if (port.net && port.net->name == ctx->id(net)) {
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ci->disconnectPort(port.name);
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pins += " " + pin_name;
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}
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};
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if (ci->type == id_DSP48E1_DSP48E1) {
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all_dsps.push_back(ci);
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auto gnd_attr = ctx->id("DSP_GND_PINS");
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auto vcc_attr = ctx->id("DSP_VCC_PINS");
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auto gnd_pins = str_or_default(ci->attrs, gnd_attr, "");
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auto vcc_pins = str_or_default(ci->attrs, vcc_attr, "");
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for (auto &port : ci->ports) {
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std::string n = port.first.str(ctx);
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if (boost::starts_with(n, "ACIN") || boost::starts_with(n, "BCIN") || boost::starts_with(n, "PCIN")) {
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if (port.second.net == nullptr)
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continue;
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if (port.second.net->name == ctx->id("$PACKER_GND_NET"))
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ci->disconnectPort(port.first);
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}
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// prjxray has extra bits for these ports to hardwire them to VCC/GND
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// as these seem to be interal to the tile,
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// this saves us from having to route those externally
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if (boost::starts_with(n, "D") ||
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boost::starts_with(n, "RSTD") ||
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// TODO: these seem to be inverted for unknown reasons
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// boost::starts_with(n, "INMODE") ||
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// boost::starts_with(n, "ALUMODE2") ||
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// boost::starts_with(n, "ALUMODE3") ||
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boost::starts_with(n, "CARRYINSEL2") ||
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boost::starts_with(n, "CED") ||
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boost::starts_with(n, "CEAD") ||
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boost::starts_with(n, "CEINMODE") ||
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boost::starts_with(n, "CEALUMODE")) {
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add_const_pin(port.second, gnd_pins, n, "$PACKER_GND_NET");
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add_const_pin(port.second, vcc_pins, n, "$PACKER_VCC_NET");
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}
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}
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ci->attrs[gnd_attr] = gnd_pins;
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ci->attrs[vcc_attr] = vcc_pins;
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}
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}
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std::vector<CellInfo *> dsp_roots;
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for (auto ci : all_dsps) {
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bool cascade_input_used = false;
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for (auto port : ci->ports) {
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if (!boost::contains(port.first.str(ctx), "CIN")) continue;
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if (port.second.net != nullptr) {
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cascade_input_used = true;
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break;
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}
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}
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if (!cascade_input_used) {
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dsp_roots.push_back(ci);
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}
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}
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for (auto root : dsp_roots) {
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root->constr_abs_z = true;
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root->constr_z = BEL_LOWER_DSP;
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walk_dsp(root, root, BEL_UPPER_DSP);
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}
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}
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NEXTPNR_NAMESPACE_END
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