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Add USR_RSTN support

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This commit is contained in:
Miodrag Milanovic 2025-01-20 08:41:36 +01:00
parent 5c142fc257
commit dbcc9b734f
6 changed files with 28 additions and 0 deletions
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2
himbaechel/uarch/gatemate/bitstream.cc
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@ -149,6 +149,8 @@ struct BitstreamBackend
} }
} }
break; break;
case id_USR_RSTN.index:
break;
default: default:
log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx), log_error("Unhandled cell %s of type %s\n", cell.second.get()->name.c_str(ctx),
cell.second->type.c_str(ctx)); cell.second->type.c_str(ctx));

3
himbaechel/uarch/gatemate/constids.inc
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@ -162,3 +162,6 @@ X(CI_FILTER_CONST)
X(CP_FILTER_CONST) X(CP_FILTER_CONST)
X(PLL_CFG_A) X(PLL_CFG_A)
X(PLL_CFG_B) X(PLL_CFG_B)
X(CC_USR_RSTN)
X(USR_RSTN)

6
himbaechel/uarch/gatemate/gatemate.cc
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@ -63,6 +63,8 @@ bool GateMateImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
return false; return false;
if (y < 2 || y > 127) if (y < 2 || y > 127)
return false; return false;
if (x == 1 && y == 66)
return false;
return true; return true;
} }
return true; return true;
@ -177,6 +179,10 @@ void GateMateImpl::postRoute()
cell->params[id_INIT_L20] = Property(0b1010, 4); cell->params[id_INIT_L20] = Property(0b1010, 4);
cell->params[id_O1] = Property(0b11, 2); cell->params[id_O1] = Property(0b11, 2);
cell->params[id_RAM_O1] = Property(1, 1); cell->params[id_RAM_O1] = Property(1, 1);
} else if (IdString(extra_data.name) == id_RAM_I1) {
cell->params[id_RAM_I1] = Property(1, 1);
} else if (IdString(extra_data.name) == id_RAM_I2) {
cell->params[id_RAM_I2] = Property(1, 1);
} else { } else {
log_error("Issue adding pass trough signal for %s.\n",IdString(extra_data.name).c_str(ctx)); log_error("Issue adding pass trough signal for %s.\n",IdString(extra_data.name).c_str(ctx));
} }

4
himbaechel/uarch/gatemate/gen/arch_gen.py
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@ -114,6 +114,10 @@ def main():
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2")) pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
pp = tt.create_pip("CPE.IN1", "CPE.RAM_O1") pp = tt.create_pip("CPE.IN1", "CPE.RAM_O1")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O1")) pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O1"))
pp = tt.create_pip("CPE.RAM_I1", "CPE.OUT1")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I1"))
pp = tt.create_pip("CPE.RAM_I2", "CPE.OUT2")
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_I2"))
for i in range(1,9): for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE") tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}") pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")

12
himbaechel/uarch/gatemate/pack.cc
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@ -559,6 +559,17 @@ void GateMatePacker::pack_pll()
ci.type = id_PLL; ci.type = id_PLL;
} }
} }
void GateMatePacker::pack_misc()
{
for (auto &cell : ctx->cells) {
CellInfo &ci = *cell.second;
if (!ci.type.in(id_CC_USR_RSTN))
continue;
ci.type = id_USR_RSTN;
}
}
void GateMatePacker::pack_constants() void GateMatePacker::pack_constants()
{ {
log_info("Packing constants..\n"); log_info("Packing constants..\n");
@ -610,6 +621,7 @@ void GateMateImpl::pack()
packer.pack_io(); packer.pack_io();
packer.pack_pll(); packer.pack_pll();
packer.pack_bufg(); packer.pack_bufg();
packer.pack_misc();
packer.pack_cpe(); packer.pack_cpe();
packer.remove_constants(); packer.remove_constants();
} }

1
himbaechel/uarch/gatemate/pack.h
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@ -32,6 +32,7 @@ struct GateMatePacker
void pack_cpe(); void pack_cpe();
void pack_bufg(); void pack_bufg();
void pack_pll(); void pack_pll();
void pack_misc();
void pack_constants(); void pack_constants();
void disconnect_if_gnd(CellInfo *cell, IdString input); void disconnect_if_gnd(CellInfo *cell, IdString input);