diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 98a7a0e4..35a460f9 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -192,7 +192,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                 bool val = (pin_type >> i) & 0x01;
                 set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
             }
-
+            set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
             auto ieren = get_ieren(bi, x, y, z);
             int iex, iey, iez;
             std::tie(iex, iey, iez) = ieren;
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 1ba40970..8e8679ee 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -256,7 +256,8 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port)
     if (port.cell->type == ctx->id("ICESTORM_LC"))
         return port.port == ctx->id("CLK");
     if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
-        return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK");
+        return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK") || port.port == ctx->id("RCLKN") ||
+               port.port == ctx->id("WCLKN");
     return false;
 }
 
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 6a6bdfaf..76e36151 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -277,6 +277,10 @@ static void pack_ram(Context *ctx)
                 if (bpos != std::string::npos) {
                     newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
                 }
+                if (pi.name == ctx->id("RCLKN"))
+                    newname = "RCLK";
+                else if (pi.name == ctx->id("WCLKN"))
+                    newname = "WCLK";
                 replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
             new_cells.push_back(std::move(packed));