ice40: Fixes for inverted clocks
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -192,7 +192,7 @@ void write_asc(const Context *ctx, std::ostream &out)
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bool val = (pin_type >> i) & 0x01;
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bool val = (pin_type >> i) & 0x01;
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set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
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set_config(ti, config.at(y).at(x), "IOB_" + std::to_string(z) + ".PINTYPE_" + std::to_string(i), val);
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}
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}
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set_config(ti, config.at(y).at(x), "NegClk", neg_trigger);
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auto ieren = get_ieren(bi, x, y, z);
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auto ieren = get_ieren(bi, x, y, z);
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int iex, iey, iez;
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int iex, iey, iez;
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std::tie(iex, iey, iez) = ieren;
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std::tie(iex, iey, iez) = ieren;
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@ -256,7 +256,8 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port)
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if (port.cell->type == ctx->id("ICESTORM_LC"))
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if (port.cell->type == ctx->id("ICESTORM_LC"))
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return port.port == ctx->id("CLK");
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return port.port == ctx->id("CLK");
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if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
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if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
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return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK");
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return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK") || port.port == ctx->id("RCLKN") ||
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port.port == ctx->id("WCLKN");
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return false;
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return false;
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}
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}
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@ -277,6 +277,10 @@ static void pack_ram(Context *ctx)
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if (bpos != std::string::npos) {
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if (bpos != std::string::npos) {
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newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
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newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2);
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}
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}
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if (pi.name == ctx->id("RCLKN"))
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newname = "RCLK";
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else if (pi.name == ctx->id("WCLKN"))
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newname = "WCLK";
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replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
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replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
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}
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}
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new_cells.push_back(std::move(packed));
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new_cells.push_back(std::move(packed));
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