Merge pull request #728 from YosysHQ/gatecat/nexus-ram
interchange/nexus: Add RAM techmap rule and a RAM test
This commit is contained in:
gatecat
GitHub
commit
ded32f3390
4
.github/workflows/interchange_ci.yml
vendored
4
.github/workflows/interchange_ci.yml
vendored
@ -114,8 +114,8 @@ jobs:
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env:
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RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
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PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
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PYTHON_INTERCHANGE_TAG: v0.0.14
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PRJOXIDE_REVISION: 82b23868d768dac9a5541331e3ddc4c4062627f7
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PYTHON_INTERCHANGE_TAG: v0.0.15
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PRJOXIDE_REVISION: 1bf30dee9c023c4c66cfc44fd0bc28addd229c89
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DEVICE: ${{ matrix.device }}
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run: |
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export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
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@ -2,3 +2,179 @@
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module INV(input A, output Z);
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LUT4 #(.INIT("0x5555")) _TECHMAP_REPLACE_ (.A(A), .B(1'b1), .C(1'b1), .D(1'b1), .Z(Z));
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endmodule
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module PDPSC16K (...);
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parameter DATA_WIDTH_W = "X36";
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parameter DATA_WIDTH_R = "X36";
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parameter OUTREG = "BYPASSED";
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parameter RESETMODE = "SYNC";
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parameter GSR = "ENABLED";
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parameter ECC = "DISABLED";
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parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
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parameter CSDECODE_W = "000";
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parameter CSDECODE_R = "000";
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parameter ASYNC_RST_RELEASE = "SYNC";
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parameter INIT_DATA = "STATIC";
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input [35:0] DI;
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input [13:0] ADW;
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input [13:0] ADR;
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input CLK;
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input CER;
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input CEW;
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input [2:0] CSW;
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input [2:0] CSR;
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input RST;
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output [35:0] DO;
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output ONEBITERR;
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output TWOBITERR;
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// TODO: this should really be a macro or otherwise dealt with more automatically
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PDPSC16K_MODE #(
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.DATA_WIDTH_W(DATA_WIDTH_W),
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.DATA_WIDTH_R(DATA_WIDTH_R),
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.OUTREG(OUTREG),
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.GSR(GSR),
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.ECC(ECC),
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.CSDECODE_W(CSDECODE_W),
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.CSDECODE_R(CSDECODE_R),
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.ASYNC_RST_RELEASE(ASYNC_RST_RELEASE),
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.INITVAL_00(INITVAL_00),
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.INITVAL_01(INITVAL_01),
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.INITVAL_02(INITVAL_02),
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.INITVAL_03(INITVAL_03),
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.INITVAL_04(INITVAL_04),
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.INITVAL_05(INITVAL_05),
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.INITVAL_06(INITVAL_06),
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.INITVAL_07(INITVAL_07),
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.INITVAL_08(INITVAL_08),
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.INITVAL_09(INITVAL_09),
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.INITVAL_0A(INITVAL_0A),
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.INITVAL_0B(INITVAL_0B),
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.INITVAL_0C(INITVAL_0C),
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.INITVAL_0D(INITVAL_0D),
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.INITVAL_0E(INITVAL_0E),
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.INITVAL_0F(INITVAL_0F),
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.INITVAL_10(INITVAL_10),
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.INITVAL_11(INITVAL_11),
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.INITVAL_12(INITVAL_12),
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.INITVAL_13(INITVAL_13),
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.INITVAL_14(INITVAL_14),
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.INITVAL_15(INITVAL_15),
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.INITVAL_16(INITVAL_16),
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.INITVAL_17(INITVAL_17),
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.INITVAL_18(INITVAL_18),
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.INITVAL_19(INITVAL_19),
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.INITVAL_1A(INITVAL_1A),
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.INITVAL_1B(INITVAL_1B),
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.INITVAL_1C(INITVAL_1C),
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.INITVAL_1D(INITVAL_1D),
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.INITVAL_1E(INITVAL_1E),
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.INITVAL_1F(INITVAL_1F),
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.INITVAL_20(INITVAL_20),
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.INITVAL_21(INITVAL_21),
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.INITVAL_22(INITVAL_22),
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.INITVAL_23(INITVAL_23),
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.INITVAL_24(INITVAL_24),
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.INITVAL_25(INITVAL_25),
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.INITVAL_26(INITVAL_26),
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.INITVAL_27(INITVAL_27),
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.INITVAL_28(INITVAL_28),
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.INITVAL_29(INITVAL_29),
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.INITVAL_2A(INITVAL_2A),
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.INITVAL_2B(INITVAL_2B),
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.INITVAL_2C(INITVAL_2C),
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.INITVAL_2D(INITVAL_2D),
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.INITVAL_2E(INITVAL_2E),
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.INITVAL_2F(INITVAL_2F),
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.INITVAL_30(INITVAL_30),
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.INITVAL_31(INITVAL_31),
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.INITVAL_32(INITVAL_32),
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.INITVAL_33(INITVAL_33),
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.INITVAL_34(INITVAL_34),
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.INITVAL_35(INITVAL_35),
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.INITVAL_36(INITVAL_36),
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.INITVAL_37(INITVAL_37),
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.INITVAL_38(INITVAL_38),
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.INITVAL_39(INITVAL_39),
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.INITVAL_3A(INITVAL_3A),
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.INITVAL_3B(INITVAL_3B),
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.INITVAL_3C(INITVAL_3C),
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.INITVAL_3D(INITVAL_3D),
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.INITVAL_3E(INITVAL_3E),
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.INITVAL_3F(INITVAL_3F),
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.INIT_DATA(INIT_DATA)
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) _TECHMAP_REPLACE_ (
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.CLK(CLK), .CER(CER), .CEW(CEW), .RST(RST),
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.CSW0(CSW[0]), .CSW1(CSW[1]), .CSW2(CSW[2]),
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.CSR0(CSR[0]), .CSR1(CSR[1]), .CSR2(CSR[2]),
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.DI0(DI[0]), .DI1(DI[1]), .DI2(DI[2]), .DI3(DI[3]), .DI4(DI[4]), .DI5(DI[5]), .DI6(DI[6]), .DI7(DI[7]), .DI8(DI[8]), .DI9(DI[9]), .DI10(DI[10]), .DI11(DI[11]), .DI12(DI[12]), .DI13(DI[13]), .DI14(DI[14]), .DI15(DI[15]), .DI16(DI[16]), .DI17(DI[17]), .DI18(DI[18]), .DI19(DI[19]), .DI20(DI[20]), .DI21(DI[21]), .DI22(DI[22]), .DI23(DI[23]), .DI24(DI[24]), .DI25(DI[25]), .DI26(DI[26]), .DI27(DI[27]), .DI28(DI[28]), .DI29(DI[29]), .DI30(DI[30]), .DI31(DI[31]), .DI32(DI[32]), .DI33(DI[33]), .DI34(DI[34]), .DI35(DI[35]),
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.ADW0(ADW[0]), .ADW1(ADW[1]), .ADW2(ADW[2]), .ADW3(ADW[3]), .ADW4(ADW[4]), .ADW5(ADW[5]), .ADW6(ADW[6]), .ADW7(ADW[7]), .ADW8(ADW[8]), .ADW9(ADW[9]), .ADW10(ADW[10]), .ADW11(ADW[11]), .ADW12(ADW[12]), .ADW13(ADW[13]),
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.ADR0(ADR[0]), .ADR1(ADR[1]), .ADR2(ADR[2]), .ADR3(ADR[3]), .ADR4(ADR[4]), .ADR5(ADR[5]), .ADR6(ADR[6]), .ADR7(ADR[7]), .ADR8(ADR[8]), .ADR9(ADR[9]), .ADR10(ADR[10]), .ADR11(ADR[11]), .ADR12(ADR[12]), .ADR13(ADR[13]),
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.DO0(DO[0]), .DO1(DO[1]), .DO2(DO[2]), .DO3(DO[3]), .DO4(DO[4]), .DO5(DO[5]), .DO6(DO[6]), .DO7(DO[7]), .DO8(DO[8]), .DO9(DO[9]), .DO10(DO[10]), .DO11(DO[11]), .DO12(DO[12]), .DO13(DO[13]), .DO14(DO[14]), .DO15(DO[15]), .DO16(DO[16]), .DO17(DO[17]), .DO18(DO[18]), .DO19(DO[19]), .DO20(DO[20]), .DO21(DO[21]), .DO22(DO[22]), .DO23(DO[23]), .DO24(DO[24]), .DO25(DO[25]), .DO26(DO[26]), .DO27(DO[27]), .DO28(DO[28]), .DO29(DO[29]), .DO30(DO[30]), .DO31(DO[31]), .DO32(DO[32]), .DO33(DO[33]), .DO34(DO[34]), .DO35(DO[35]),
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.ONEBITERR(ONEBITERR), .TWOBITERR(TWOBITERR),
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);
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endmodule
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@ -6,3 +6,4 @@ add_subdirectory(ff)
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add_subdirectory(lut)
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add_subdirectory(lut_nexus)
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add_subdirectory(lutram)
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add_subdirectory(ram_nexus)
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10
fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt
Normal file
10
fpga_interchange/examples/tests/ram_nexus/CMakeLists.txt
Normal file
@ -0,0 +1,10 @@
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add_interchange_group_test(
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name ram_nexus
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family ${family}
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board_list lifcl40evn
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tcl run_nexus.tcl
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sources ram_nexus.v
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techmap ../../remap_nexus.v
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skip_dcp
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)
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57
fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc
Normal file
57
fpga_interchange/examples/tests/ram_nexus/lifcl40evn.xdc
Normal file
@ -0,0 +1,57 @@
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set_property PACKAGE_PIN L13 [get_ports clk]
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set_property PACKAGE_PIN E17 [get_ports led[0]]
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set_property PACKAGE_PIN F13 [get_ports led[1]]
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set_property PACKAGE_PIN G13 [get_ports led[2]]
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set_property PACKAGE_PIN F14 [get_ports led[3]]
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set_property PACKAGE_PIN L16 [get_ports led[4]]
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set_property PACKAGE_PIN L15 [get_ports led[5]]
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set_property PACKAGE_PIN L20 [get_ports led[6]]
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set_property PACKAGE_PIN L19 [get_ports led[7]]
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set_property PACKAGE_PIN R17 [get_ports led[8]]
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set_property PACKAGE_PIN R18 [get_ports led[9]]
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set_property PACKAGE_PIN U20 [get_ports led[10]]
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set_property PACKAGE_PIN T20 [get_ports led[11]]
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set_property PACKAGE_PIN W20 [get_ports led[12]]
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set_property PACKAGE_PIN V20 [get_ports led[13]]
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set_property PACKAGE_PIN G14 [get_ports pb0]
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set_property PACKAGE_PIN G15 [get_ports pb1]
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set_property PACKAGE_PIN N14 [get_ports sw[0]]
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set_property PACKAGE_PIN M14 [get_ports sw[1]]
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set_property PACKAGE_PIN M16 [get_ports sw[2]]
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set_property PACKAGE_PIN M15 [get_ports sw[3]]
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set_property PACKAGE_PIN N15 [get_ports sw[4]]
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set_property PACKAGE_PIN N16 [get_ports sw[5]]
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set_property PACKAGE_PIN M17 [get_ports sw[6]]
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set_property PACKAGE_PIN M18 [get_ports sw[7]]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
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set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
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set_property IOSTANDARD LVCMOS33 [get_ports pb0]
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set_property IOSTANDARD LVCMOS33 [get_ports pb1]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
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set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
|
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123
fpga_interchange/examples/tests/ram_nexus/ram_nexus.v
Normal file
123
fpga_interchange/examples/tests/ram_nexus/ram_nexus.v
Normal file
@ -0,0 +1,123 @@
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module ram0(
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// Write port
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input wrclk,
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input [7:0] di,
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input wren,
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input [5:0] wraddr,
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// Read port
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input rdclk,
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input rden,
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input [5:0] rdaddr,
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output reg [7:0] do);
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(* syn_ramstyle = "block_ram" *) reg [7:0] ram[0:63];
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initial begin
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ram[0] = 8'b00000001;
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||||
ram[1] = 8'b10101010;
|
||||
ram[2] = 8'b01010101;
|
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ram[3] = 8'b11111111;
|
||||
ram[4] = 8'b11110000;
|
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ram[5] = 8'b00001111;
|
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ram[6] = 8'b11001100;
|
||||
ram[7] = 8'b00110011;
|
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ram[8] = 8'b00000010;
|
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ram[9] = 8'b00000100;
|
||||
end
|
||||
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always @ (posedge wrclk) begin
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||||
if(wren == 1) begin
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||||
ram[wraddr] <= di;
|
||||
end
|
||||
end
|
||||
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||||
always @ (posedge rdclk) begin
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||||
if(rden == 1) begin
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||||
do <= ram[rdaddr];
|
||||
end
|
||||
end
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||||
|
||||
endmodule
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||||
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module top (
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input wire clk,
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||||
|
||||
input wire pb0,
|
||||
input wire pb1,
|
||||
|
||||
input wire [7:0] sw,
|
||||
output wire [13:0] led
|
||||
);
|
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wire bufclk;
|
||||
DCC gbuf_i(.CLKI(clk), .CLKO(bufclk));
|
||||
|
||||
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||||
wire rden;
|
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reg wren;
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wire [5:0] rdaddr;
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||||
wire [5:0] wraddr;
|
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wire [7:0] di;
|
||||
wire [7:0] do;
|
||||
ram0 ram(
|
||||
.wrclk(bufclk),
|
||||
.di(di),
|
||||
.wren(wren),
|
||||
.wraddr(wraddr),
|
||||
.rdclk(bufclk),
|
||||
.rden(rden),
|
||||
.rdaddr(rdaddr),
|
||||
.do(do)
|
||||
);
|
||||
|
||||
reg [5:0] address_reg;
|
||||
reg [7:0] data_reg;
|
||||
reg [7:0] out_reg;
|
||||
|
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assign rdaddr = address_reg;
|
||||
assign wraddr = address_reg;
|
||||
|
||||
// input_mode == 00 -> in[3:0] -> address_reg
|
||||
// input_mode == 01 -> in[3:0] -> data_reg[3:0]
|
||||
// input_mode == 10 -> in[3:0] -> data_reg[7:4]
|
||||
// input_mode == 11 -> data_reg -> ram[address_reg]
|
||||
wire [1:0] input_mode;
|
||||
|
||||
// WE == 0 -> address_reg and data_reg unchanged.
|
||||
// WE == 1 -> address_reg or data_reg is updated because on input_mode.
|
||||
wire we;
|
||||
|
||||
assign input_mode[0] = ~sw[6];
|
||||
assign input_mode[1] = ~sw[7];
|
||||
|
||||
assign we = ~pb0;
|
||||
assign led = ~{address_reg, out_reg};
|
||||
assign di = data_reg;
|
||||
assign rden = 1;
|
||||
|
||||
initial begin
|
||||
wren = 1'b0;
|
||||
address_reg = 10'b0;
|
||||
data_reg = 16'b0;
|
||||
out_reg = 16'b0;
|
||||
end
|
||||
|
||||
always @ (posedge bufclk) begin
|
||||
out_reg <= do;
|
||||
|
||||
if(we == 1) begin
|
||||
if(input_mode == 0) begin
|
||||
address_reg <= ~sw[5:0];
|
||||
wren <= 0;
|
||||
end else if(input_mode == 1) begin
|
||||
data_reg[3:0] <= ~sw[3:0];
|
||||
wren <= 0;
|
||||
end else if(input_mode == 2) begin
|
||||
data_reg[7:4] <= ~sw[3:0];
|
||||
wren <= 0;
|
||||
end else if(input_mode == 3) begin
|
||||
wren <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
15
fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl
Normal file
15
fpga_interchange/examples/tests/ram_nexus/run_nexus.tcl
Normal file
@ -0,0 +1,15 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_nexus -nolutram -nowidelut -noccu2 -nodsp
|
||||
techmap -max_iter 1 -map $::env(TECHMAP)
|
||||
|
||||
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
|
||||
# net.
|
||||
opt_expr -undriven
|
||||
opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json $::env(OUT_JSON)
|
||||
Loading…
Reference in New Issue
Block a user