caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clangformat

Browse Source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-03-09 17:12:59 +00:00
parent 5ff701d45e
commit df7e26c1aa
4 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
common/parallel_refine.cc
View File

@ -23,8 +23,8 @@
#if !defined(__wasm)
#include "fast_bels.h"
#include "timing.h"
#include "scope_lock.h"
#include "timing.h"
#include <chrono>
#include <mutex>
@ -952,10 +952,7 @@ NEXTPNR_NAMESPACE_END
NEXTPNR_NAMESPACE_BEGIN
bool parallel_refine(Context *ctx, ParallelRefineCfg cfg)
{
log_abort();
}
bool parallel_refine(Context *ctx, ParallelRefineCfg cfg) { log_abort(); }
NEXTPNR_NAMESPACE_END

2
fpga_interchange/arch.h
View File

@ -1134,7 +1134,7 @@ struct Arch : ArchAPI<ArchRanges>
IdString vcc_cell_pin;
std::vector<std::vector<LutElement>> lut_elements;
dict<IdString, const LutCellPOD *> lut_cells;
// Defines the max number of LUT cells in a site and LUT pins
// to allow a correct functioning of the site lut mapping cache
int max_lut_cells;

6
fpga_interchange/site_lut_mapping_cache.h
View File

@ -51,9 +51,9 @@ struct SiteLutMappingKey
}
};
int32_t tileType; // Tile type
int32_t siteType; // Site type in that tile type
size_t numCells; // LUT cell count
int32_t tileType; // Tile type
int32_t siteType; // Site type in that tile type
size_t numCells; // LUT cell count
std::vector<Cell> cells; // LUT cell data
unsigned int hash_; // Precomputed hash

3
nexus/pack.cc
View File

@ -883,7 +883,8 @@ struct NexusPacker
for (size_t i = 0; i < std::min<size_t>(clk_fanout.size(), available_globals); i++) {
NetInfo *net = ctx->nets.at(clk_fanout.at(i).second).get();
log_info(" promoting clock net '%s'\n", ctx->nameOf(net));
insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO, [&](const PortRef &port) { return port.cell->type != id_DCC; });
insert_buffer(net, id_DCC, "glb_clk", id_CLKI, id_CLKO,
[&](const PortRef &port) { return port.cell->type != id_DCC; });
}
}