machxo2: Add pip and wire info into facade_import.
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@ -77,6 +77,11 @@ def write_database(dev_name, chip, rg, endianness):
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bba.u16(loc.x, "%s.x" % sym_name)
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bba.u16(loc.y, "%s.y" % sym_name)
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# Use Lattice naming conventions, so convert to 1-based col indexing.
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def get_wire_name(loc, idx):
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tile = rg.tiles[loc]
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return "R{}C{}_{}".format(loc.y, loc.x + 1, rg.to_str(tile.wires[idx].name))
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# Before doing anything, ensure sorted routing graph iteration matches
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# y, x
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tile_iter = list(sorted(rg.tiles, key=lambda l : (l.key().y, l.key().x)))
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@ -109,9 +114,54 @@ def write_database(dev_name, chip, rg, endianness):
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if len(t.arcs) > 0:
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bba.l("loc%d_%d_pips" % (l.y, l.x), "PipInfoPOD")
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for arc in t.arcs:
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write_loc(arc.srcWire.rel, "src")
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write_loc(arc.sinkWire.rel, "dst")
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bba.u32(arc.srcWire.id, "src_idx {}".format(get_wire_name(arc.srcWire.rel, arc.srcWire.id)))
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bba.u32(arc.sinkWire.id, "dst_idx {}".format(get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)))
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src_name = get_wire_name(arc.srcWire.rel, arc.srcWire.id)
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snk_name = get_wire_name(arc.sinkWire.rel, arc.sinkWire.id)
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# bba.u32(get_pip_class(src_name, snk_name), "timing_class")
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bba.u16(get_tiletype_index(rg.to_str(arc.tiletype)), "tile_type")
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cls = arc.cls
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bba.u8(arc.cls, "pip_type")
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bba.u8(0, "padding")
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if len(t.wires) > 0:
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for wire_idx in range(len(t.wires)):
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wire = t.wires[wire_idx]
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if len(wire.arcsDownhill) > 0:
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bba.l("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
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for dp in wire.arcsDownhill:
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write_loc(dp.rel, "rel_loc")
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bba.u32(dp.id, "index")
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if len(wire.arcsUphill) > 0:
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bba.l("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx), "PipLocatorPOD")
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for up in wire.arcsUphill:
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write_loc(up.rel, "rel_loc")
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bba.u32(up.id, "index")
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if len(wire.belPins) > 0:
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bba.l("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx), "BelPortPOD")
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for bp in wire.belPins:
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write_loc(bp.bel.rel, "rel_bel_loc")
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bba.u32(bp.bel.id, "bel_index")
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# bba.u32(constids[rg.to_str(bp.pin)], "port")
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bba.l("loc%d_%d_wires" % (l.y, l.x), "WireInfoPOD")
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for wire_idx in range(len(t.wires)):
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wire = t.wires[wire_idx]
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bba.s(rg.to_str(wire.name), "name")
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# bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
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# if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
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# bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
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# else:
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bba.u32(0, "tile_wire")
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bba.u32(len(wire.arcsUphill), "num_uphill")
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bba.u32(len(wire.arcsDownhill), "num_downhill")
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bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
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bba.r("loc%d_%d_wire%d_downpips" % (l.y, l.x, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
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bba.u32(len(wire.belPins), "num_bel_pins")
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bba.r("loc%d_%d_wire%d_belpins" % (l.y, l.x, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
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if len(t.bels) > 0:
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bba.l("loc%d_%d_bels" % (l.y, l.x), "BelInfoPOD")
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