Fix blinky.sh and blinky_sim.sh

xc7/blinky.sh

@@ -1,14 +1,6 @@
 #!/bin/bash
 set -ex
 yosys blinky.ys
-../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 150
+../nextpnr-xc7 --json blinky.json --pcf blinky.pcf --xdl blinky.xdl --freq 125
 xdl -xdl2ncd blinky.xdl
 bitgen -w blinky.ncd -g UnconstrainedPins:Allow
-trce blinky.ncd -v 10
-#netgen -ofmt verilog -w blinky.ncd blinky_chip.v -tm blinky -insert_glbl true
-#iverilog -o blinky_tb blinky_chip.v blinky_tb.v -y/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/simprims/
-#vvp -N ./blinky_tb
-
-#xdl -xdl2ncd blinky.xdl -nopips blinky_map.ncd
-#par -w blinky_map.ncd blinky_par.ncd blinky.pcf
-#bitgen -w blinky_par.ncd -g UnconstrainedPins:Allow

xc7/blinky.v

@@ -5,8 +5,6 @@ module blinky (
     output led2,
     output led3
 );
-    //`include "ps7.vh"
-
     BUFGCTRL clk_gb (
         .I0(clki),
         .CE0(1'b1),
@@ -19,7 +17,7 @@ module blinky (
     );
 
     localparam BITS = 4;
-    localparam LOG2DELAY = 23;
+    parameter LOG2DELAY = 23;
 
     reg [BITS+LOG2DELAY-1:0] counter = 0;
     reg [BITS-1:0] outcnt;
@@ -29,5 +27,5 @@ module blinky (
         outcnt <= counter >> LOG2DELAY;
     end
 
-    assign {led0, led1, led2, led3} = outcnt /*^ (outcnt >> 1)*/;
+    assign {led0, led1, led2, led3} = outcnt ^ (outcnt >> 1);
 endmodule

xc7/blinky_sim.ys

@@ -0,0 +1,54 @@
+read_verilog blinky.v
+chparam -set LOG2DELAY 0
+
+#synth_xilinx -top blinky
+
+#begin:
+    read_verilog -lib +/xilinx/cells_sim.v
+    read_verilog -lib +/xilinx/cells_xtra.v
+#    read_verilog -lib +/xilinx/brams_bb.v
+#    read_verilog -lib +/xilinx/drams_bb.v
+    hierarchy -check -top blinky
+
+#flatten:     (only if -flatten)
+    proc
+    flatten
+
+#coarse:
+    synth -run coarse
+
+#bram:
+#    memory_bram -rules +/xilinx/brams.txt
+#    techmap -map +/xilinx/brams_map.v
+#
+#dram:
+#    memory_bram -rules +/xilinx/drams.txt
+#    techmap -map +/xilinx/drams_map.v
+
+fine:
+    opt -fast -full
+    memory_map
+    dffsr2dff
+#    dff2dffe
+    opt -full
+    techmap -map +/techmap.v #-map +/xilinx/arith_map.v
+    opt -fast
+
+map_luts:
+    abc -luts 2:2,3,6:5 #,10,20 [-dff]
+    clean
+
+map_cells:
+    techmap -map +/xilinx/cells_map.v
+    dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
+    clean
+
+check:
+    hierarchy -check
+    stat
+    check -noinit
+
+#edif:     (only if -edif)
+#    write_edif <file-name>
+
+write_json blinky.json

xc7/blinky_tb.v

@@ -1,25 +0,0 @@
-module blinky_tb;
-    reg clk;
-    always #5 clk = (clk === 1'b0);
-
-    wire led0, led1, led2, led3;
-
-    blinky uut (
-        .\clki.PAD.PAD (clk),
-        .\led0.OUTBUF.OUT (led0),
-        .\led1.OUTBUF.OUT (led1),
-        .\led2.OUTBUF.OUT (led2),
-        .\led3.OUTBUF.OUT (led3)
-    );
-
-    initial begin
-        // $dumpfile("blinky_tb.vcd");
-        // $dumpvars(0, blinky_tb);
-        $monitor(led0, led1, led2, led3);
-        //repeat (10) begin
-        //    repeat (900000) @(posedge clk);
-        //    $display(led0, led1, led2, led3);
-        //end
-        //$finish;
-    end
-endmodule

xc7/blinky_tb.vhd

@@ -0,0 +1,25 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity testbench is
+end entity;
+architecture rtl of testbench is
+    signal clk : STD_LOGIC;
+    signal led : STD_LOGIC_VECTOR(3 downto 0);
+begin
+    process begin
+        clk <= '0';
+        wait for 4 ns;
+        clk <= '1';
+        wait for 4 ns;
+    end process;
+
+    uut: entity work.name port map(clki_PAD_PAD => clk, led0_OUTBUF_OUT => led(0), led1_OUTBUF_OUT => led(1), led2_OUTBUF_OUT => led(2), led3_OUTBUF_OUT => led(3));
+
+process
+begin
+report std_logic'image(led(3)) & std_logic'image(led(2)) & std_logic'image(led(1)) & std_logic'image(led(0));
+wait on led;
+end process;
+
+end rtl;