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Add Arch::getBelPins() to generic and iCE40 archs

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-07-22 12:08:52 +02:00
parent b60c9485d2
commit e13fc7edab
4 changed files with 25 additions and 0 deletions
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7
generic/arch.cc
View File

@ -226,6 +226,13 @@ BelPin Arch::getBelPinUphill(WireId wire) const { return wires.at(wire).uphill_b
const std::vector<BelPin> &Arch::getBelPinsDownhill(WireId wire) const { return wires.at(wire).downhill_bel_pins; }
std::vector<PortPin> Arch::getBelPins(BelId bel) const
{
std::vector<PortPin> ret;
for (auto &it : bels.at(bel).pins)
ret.push_back(it.first);
}
// ---------------------------------------------------------------
WireId Arch::getWireByName(IdString name) const

1
generic/arch.h
View File

@ -150,6 +150,7 @@ struct Arch : BaseCtx
PortType getBelPinType(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED;
const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED;
std::vector<PortPin> getBelPins(BelId bel) const;
WireId getWireByName(IdString name) const;
IdString getWireName(WireId wire) const;

15
ice40/arch.cc
View File

@ -340,6 +340,21 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
return ret;
}
std::vector<PortPin> Arch::getBelPins(BelId bel) const
{
std::vector<PortPin> ret;
NPNR_ASSERT(bel != BelId());
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++)
ret.push_back(bel_wires[i].port);
return ret;
}
// -----------------------------------------------------------------------
WireId Arch::getWireByName(IdString name) const

2
ice40/arch.h
View File

@ -494,6 +494,8 @@ struct Arch : BaseCtx
return range;
}
std::vector<PortPin> getBelPins(BelId bel) const;
// -------------------------------------------------
WireId getWireByName(IdString name) const;