Merge pull request #686 from YosysHQ/gatecat/interchange-macro

interchange: Add macro expansion

.github/workflows/interchange_ci.yml

@@ -114,7 +114,7 @@ jobs:
       env:
         RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
         PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
-        PYTHON_INTERCHANGE_TAG: v0.0.12
+        PYTHON_INTERCHANGE_TAG: v0.0.13
         PRJOXIDE_REVISION: b5d88c3491770559c3c10cccb1651db65ab061b1
         DEVICE: ${{ matrix.device }}
       run: |

3rdparty/fpga-interchange-schema

@@ -1 +1 @@
-Subproject commit 7e850b6bb0d5c4b7e25e94ce9fbbd68a0dbc1e1a
+Subproject commit eb8ca042ba4d0a3768713ef733d7a85ffad59a94

fpga_interchange/arch.cc

@@ -770,6 +770,7 @@ bool Arch::pack()
     merge_constant_nets();
     pack_ports();
     pack_default_conns();
+    expand_macros();
     return true;
 }
 

fpga_interchange/arch.h

@@ -1124,6 +1124,8 @@ struct Arch : ArchAPI<ArchRanges>
 
     const DefaultCellConnsPOD *get_default_conns(IdString cell_type) const;
     void pack_default_conns();
+
+    void expand_macros();
 };
 
 NEXTPNR_NAMESPACE_END

fpga_interchange/chipdb.h

@@ -34,7 +34,7 @@ NEXTPNR_NAMESPACE_BEGIN
  * kExpectedChipInfoVersion
  */
 
-static constexpr int32_t kExpectedChipInfoVersion = 9;
+static constexpr int32_t kExpectedChipInfoVersion = 10;
 
 // Flattened site indexing.
 //
@@ -332,6 +332,76 @@ NPNR_PACKED_STRUCT(struct GlobalCellPOD {
     RelSlice<GlobalCellPinPOD> pins;
 });
 
+NPNR_PACKED_STRUCT(struct MacroParameterPOD {
+    int32_t key;   // constid
+    int32_t value; // constid
+});
+
+enum MacroParamRuleType
+{
+    PARAM_MAP_COPY = 0,  // copy parameter value
+    PARAM_MAP_SLICE = 1, // take a slice of bits
+    PARAM_MAP_TABLE = 2, // lookup strings in table
+};
+
+NPNR_PACKED_STRUCT(struct MacroParamMapRulePOD {
+    // name of parameter on parent primitive
+    int32_t prim_param; // constid
+    // name of instance to set parameter on
+    int32_t inst_name; // constid
+    // name of parameter on macro expansion instance
+    int32_t inst_param; // constid
+    // type of mapping to use to derive new value
+    int32_t rule_type; // MacroParamRuleType
+    // for slice mappings, the bits to collect
+    RelSlice<uint32_t> slice_bits;
+    // for table mappings, the lookup table to use
+    RelSlice<MacroParameterPOD> map_table;
+});
+
+NPNR_PACKED_STRUCT(struct MacroCellInstPOD {
+    int32_t name; // instance name constid
+    int32_t type; // instance type constid
+    // parameters to set on cell
+    RelSlice<MacroParameterPOD> parameters;
+});
+
+NPNR_PACKED_STRUCT(struct MacroPortInstPOD {
+    // name of the cell instance the port is on; or 0/'' for top level ports
+    int32_t instance;
+    // name of the port
+    int32_t port;
+    // direction of the port
+    int32_t dir;
+});
+
+NPNR_PACKED_STRUCT(struct MacroNetPOD {
+    // name of the net
+    int32_t name;
+    // ports on the net
+    RelSlice<MacroPortInstPOD> ports;
+});
+
+NPNR_PACKED_STRUCT(struct MacroPOD {
+    // macro name
+    int32_t name;
+    // cell instances inside macro
+    RelSlice<MacroCellInstPOD> cell_insts;
+    // nets inside macro
+    RelSlice<MacroNetPOD> nets;
+});
+
+NPNR_PACKED_STRUCT(struct MacroExpansionPOD {
+    // primitive name to match
+    int32_t prim_name;
+    // macro name to expand to
+    int32_t macro_name;
+    // list of parameters to (optionally) match
+    RelSlice<MacroParameterPOD> param_matches;
+    // how to derive parameters for expansion instances
+    RelSlice<MacroParamMapRulePOD> param_rules;
+});
+
 NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelPtr<char> name;
     RelPtr<char> generator;
@@ -347,6 +417,10 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     RelSlice<WireTypePOD> wire_types;
     RelSlice<GlobalCellPOD> global_cells;
 
+    // Macro related data
+    RelSlice<MacroPOD> macros;
+    RelSlice<MacroExpansionPOD> macro_rules;
+
     // BEL bucket constids.
     RelSlice<int32_t> bel_buckets;
 

fpga_interchange/examples/tests/CMakeLists.txt

@@ -5,3 +5,4 @@ add_subdirectory(ram)
 add_subdirectory(ff)
 add_subdirectory(lut)
 add_subdirectory(lut_nexus)
+add_subdirectory(lutram)

fpga_interchange/examples/tests/lutram/CMakeLists.txt

@@ -0,0 +1,8 @@
+add_interchange_group_test(
+    name lutram
+    family ${family}
+    board_list basys3
+    tcl run.tcl
+    sources lutram.v
+)
+

fpga_interchange/examples/tests/lutram/basys3.pcf

@@ -0,0 +1,41 @@
+# basys3 100 MHz CLK
+set_io clk W5
+
+set_io tx A18
+set_io rx B18
+#
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_io sw[0] V17
+set_io sw[1] V16
+set_io sw[2] W16
+set_io sw[3] W17
+set_io sw[4] W15
+set_io sw[5] V15
+set_io sw[6] W14
+set_io sw[7] W13
+set_io sw[8] V2
+set_io sw[9] T3
+set_io sw[10] T2
+set_io sw[11] R3
+set_io sw[12] W2
+set_io sw[13] U1
+set_io sw[14] T1
+set_io sw[15] R2
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_io led[0] U16
+set_io led[1] E19
+set_io led[2] U19
+set_io led[3] V19
+set_io led[4] W18
+set_io led[5] U15
+set_io led[6] U14
+set_io led[7] V14
+set_io led[8] V13
+set_io led[9] V3
+set_io led[10] W3
+set_io led[11] U3
+set_io led[12] P3
+set_io led[13] N3
+set_io led[14] P1
+set_io led[15] L1

fpga_interchange/examples/tests/lutram/basys3.xdc

@@ -0,0 +1,80 @@
+# basys3 100 MHz CLK
+set_property PACKAGE_PIN W5 [get_ports clk]
+
+set_property PACKAGE_PIN A18 [get_ports tx]
+set_property PACKAGE_PIN B18 [get_ports rx]
+#
+# in[0:15] correspond with SW0-SW15 on the basys3
+set_property PACKAGE_PIN V17 [get_ports sw[0]]
+set_property PACKAGE_PIN V16 [get_ports sw[1]]
+set_property PACKAGE_PIN W16 [get_ports sw[2]]
+set_property PACKAGE_PIN W17 [get_ports sw[3]]
+set_property PACKAGE_PIN W15 [get_ports sw[4]]
+set_property PACKAGE_PIN V15 [get_ports sw[5]]
+set_property PACKAGE_PIN W14 [get_ports sw[6]]
+set_property PACKAGE_PIN W13 [get_ports sw[7]]
+set_property PACKAGE_PIN V2  [get_ports sw[8]]
+set_property PACKAGE_PIN T3  [get_ports sw[9]]
+set_property PACKAGE_PIN T2  [get_ports sw[10]]
+set_property PACKAGE_PIN R3  [get_ports sw[11]]
+set_property PACKAGE_PIN W2  [get_ports sw[12]]
+set_property PACKAGE_PIN U1  [get_ports sw[13]]
+set_property PACKAGE_PIN T1  [get_ports sw[14]]
+set_property PACKAGE_PIN R2  [get_ports sw[15]]
+
+# out[0:15] correspond with LD0-LD15 on the basys3
+set_property PACKAGE_PIN U16 [get_ports led[0]]
+set_property PACKAGE_PIN E19 [get_ports led[1]]
+set_property PACKAGE_PIN U19 [get_ports led[2]]
+set_property PACKAGE_PIN V19 [get_ports led[3]]
+set_property PACKAGE_PIN W18 [get_ports led[4]]
+set_property PACKAGE_PIN U15 [get_ports led[5]]
+set_property PACKAGE_PIN U14 [get_ports led[6]]
+set_property PACKAGE_PIN V14 [get_ports led[7]]
+set_property PACKAGE_PIN V13 [get_ports led[8]]
+set_property PACKAGE_PIN V3  [get_ports led[9]]
+set_property PACKAGE_PIN W3  [get_ports led[10]]
+set_property PACKAGE_PIN U3  [get_ports led[11]]
+set_property PACKAGE_PIN P3  [get_ports led[12]]
+set_property PACKAGE_PIN N3  [get_ports led[13]]
+set_property PACKAGE_PIN P1  [get_ports led[14]]
+set_property PACKAGE_PIN L1  [get_ports led[15]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+
+set_property IOSTANDARD LVCMOS33 [get_ports tx]
+set_property IOSTANDARD LVCMOS33 [get_ports rx]
+#
+set_property IOSTANDARD LVCMOS33 [get_ports sw[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[7]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[8]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[9]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[10]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[11]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[12]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[13]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[14]]
+set_property IOSTANDARD LVCMOS33 [get_ports sw[15]]
+
+set_property IOSTANDARD LVCMOS33 [get_ports led[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[5]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[6]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[7]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[8]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[9]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[10]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[11]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[12]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[13]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[14]]
+set_property IOSTANDARD LVCMOS33 [get_ports led[15]]

fpga_interchange/examples/tests/lutram/lutram.v

@@ -0,0 +1,24 @@
+module top (
+    input  wire clk,
+
+    input  wire rx,
+    output wire tx,
+
+    input  wire [15:0] sw,
+    output wire [15:0] led
+);
+    RAM128X1D #(
+        .INIT(128'hFFEEDDCCBBAA99887766554433221100)
+    ) ram_i (
+        .WCLK(clk),
+        .A(sw[6:0]),
+        .DPRA(sw[13:7]),
+        .WE(sw[14]),
+        .D(sw[15]),
+        .SPO(led[0]),
+        .DPO(led[1]),
+    );
+
+    assign led[15:2] = 14'b0;
+    assign tx = rx;
+endmodule

fpga_interchange/examples/tests/lutram/run.tcl

@@ -0,0 +1,17 @@
+yosys -import
+
+foreach src $::env(SOURCES) {
+    read_verilog $src
+}
+
+synth_xilinx -flatten -nolutram -nowidelut -nosrl -nocarry -nodsp
+techmap -map $::env(TECHMAP)
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)

fpga_interchange/macros.cc

@@ -0,0 +1,161 @@
+/*
+ *  nextpnr -- Next Generation Place and Route
+ *
+ *  Copyright (C) 2021  Symbiflow Authors
+ *
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "design_utils.h"
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+static const MacroPOD *lookup_macro(const ChipInfoPOD *chip, IdString cell_type)
+{
+    for (const auto &macro : chip->macros) {
+        if (IdString(macro.name) == cell_type)
+            return &macro;
+    }
+    return nullptr;
+}
+
+static const MacroExpansionPOD *lookup_macro_rules(const ChipInfoPOD *chip, IdString cell_type)
+{
+    for (const auto &rule : chip->macro_rules) {
+        if (IdString(rule.prim_name) == cell_type)
+            return &rule;
+    }
+    return nullptr;
+}
+
+static IdString derived_name(Context *ctx, IdString base_name, IdString suffix)
+{
+    return ctx->id(stringf("%s/%s", base_name.c_str(ctx), suffix.c_str(ctx)));
+}
+
+void Arch::expand_macros()
+{
+    // Make up a list of cells, so we don't have modify-while-iterating issues
+    Context *ctx = getCtx();
+    std::vector<CellInfo *> cells;
+    for (auto cell : sorted(ctx->cells))
+        cells.push_back(cell.second);
+
+    std::vector<CellInfo *> next_cells;
+
+    do {
+        // Expand cells
+        for (auto cell : cells) {
+            // TODO: consult exception map
+            const MacroExpansionPOD *exp = lookup_macro_rules(chip_info, cell->type);
+            const MacroPOD *macro = lookup_macro(chip_info, exp ? IdString(exp->macro_name) : cell->type);
+            if (macro == nullptr)
+                continue;
+            // Create child instances
+            for (const auto &inst : macro->cell_insts) {
+                CellInfo *inst_cell =
+                        ctx->createCell(derived_name(ctx, cell->name, IdString(inst.name)), IdString(inst.type));
+                for (const auto &param : inst.parameters) {
+                    inst_cell->params[IdString(param.key)] = IdString(param.value).str(ctx);
+                }
+                next_cells.push_back(inst_cell);
+            }
+            // Create and connect nets
+            for (const auto &net_data : macro->nets) {
+                NetInfo *net = nullptr;
+                // If there is a top level port, use that as the net
+                for (const auto &net_port : net_data.ports) {
+                    if (net_port.instance != 0)
+                        continue;
+                    // TODO: case of multiple top level ports on the same net?
+                    NPNR_ASSERT(net == nullptr);
+                    // Use the corresponding pre-expansion port net
+                    net = get_net_or_empty(cell, IdString(net_port.port));
+                    // Disconnect the original port pre-expansion
+                    disconnect_port(ctx, cell, IdString(net_port.port));
+                }
+                // If not on a top level port, create a new net
+                if (net == nullptr)
+                    net = ctx->createNet(derived_name(ctx, cell->name, IdString(net_data.name)));
+                // Create and connect instance ports
+                for (const auto &net_port : net_data.ports) {
+                    if (net_port.instance == 0)
+                        continue;
+                    IdString port_name(net_port.port);
+                    CellInfo *inst_cell =
+                            ctx->cells.at(derived_name(ctx, cell->name, IdString(net_port.instance))).get();
+                    inst_cell->ports[port_name].name = port_name;
+                    inst_cell->ports[port_name].type = PortType(net_port.dir);
+                    connect_port(ctx, net, inst_cell, port_name);
+                }
+            }
+
+            if (exp != nullptr) {
+                // Convert parameters, according to the exception rules
+                for (const auto &param_rule : exp->param_rules) {
+                    IdString prim_param(param_rule.prim_param);
+                    if (!cell->params.count(prim_param))
+                        continue;
+                    const auto &prim_param_val = cell->params.at(prim_param);
+                    IdString inst_name = derived_name(ctx, cell->name, IdString(param_rule.inst_name));
+                    CellInfo *inst_cell = ctx->cells.at(inst_name).get();
+                    IdString inst_param(param_rule.inst_param);
+                    if (param_rule.rule_type == PARAM_MAP_COPY) {
+                        inst_cell->params[inst_param] = prim_param_val;
+                    } else if (param_rule.rule_type == PARAM_MAP_SLICE) {
+                        auto prim_bits = cell_parameters.parse_int_like(ctx, cell->type, prim_param, prim_param_val);
+                        Property value(0, param_rule.slice_bits.ssize());
+                        for (int i = 0; i < param_rule.slice_bits.ssize(); i++) {
+                            size_t bit = param_rule.slice_bits[i];
+                            if (bit >= prim_bits.size())
+                                continue;
+                            value.str.at(i) = prim_bits.get(bit) ? Property::S1 : Property::S0;
+                        }
+                        inst_cell->params[inst_param] = value;
+                    } else if (param_rule.rule_type == PARAM_MAP_TABLE) {
+                        const std::string &prim_str = prim_param_val.as_string();
+                        IdString prim_id = ctx->id(prim_str);
+                        for (auto &tbl_entry : param_rule.map_table) {
+                            if (IdString(tbl_entry.key) == prim_id) {
+                                inst_cell->params[inst_param] = IdString(tbl_entry.value).str(ctx);
+                                break;
+                            }
+                        }
+                        if (!inst_cell->params.count(inst_param))
+                            log_error("Unsupported value '%s' for property '%s' of cell %s:%s\n", prim_str.c_str(),
+                                      ctx->nameOf(prim_param), ctx->nameOf(cell), ctx->nameOf(cell->type));
+                    }
+                }
+            }
+
+            // Remove the now-expanded cell, but first make sure we don't leave behind any dangling references
+            for (const auto &port : cell->ports)
+                if (port.second.net != nullptr)
+                    log_error("Macro expansion of %s:%s left dangling port %s.", ctx->nameOf(cell),
+                              ctx->nameOf(cell->type), ctx->nameOf(port.first));
+            ctx->cells.erase(cell->name);
+        }
+
+        // Iterate until no more expansions are possible
+        // The next iteration only needs to look at cells created in this iteration
+        std::swap(next_cells, cells);
+        next_cells.clear();
+    } while (!cells.empty());
+}
+
+NEXTPNR_NAMESPACE_END

fpga_interchange/site_arch.cc

@@ -136,6 +136,8 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
     bool have_vcc_pins = false;
     for (CellInfo *cell : site_info->cells_in_site) {
         for (const auto &pin_pair : cell->cell_bel_pins) {
+            if (!cell->ports.count(pin_pair.first))
+                continue;
             const PortInfo &port = cell->ports.at(pin_pair.first);
             if (port.net != nullptr) {
                 nets.emplace(port.net, SiteNetInfo{port.net});

fpga_interchange/site_router.cc

@@ -59,8 +59,7 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
         BelId bel = cell->bel;
         for (const auto &pin_pair : cell->cell_bel_pins) {
             if (!cell->ports.count(pin_pair.first))
-                log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
+                continue;
-                          pin_pair.first.c_str(ctx));
             const PortInfo &port = cell->ports.at(pin_pair.first);
             NPNR_ASSERT(port.net != nullptr);