diff --git a/common/kernel/arch_pybindings_shared.h b/common/kernel/arch_pybindings_shared.h index b3dc0506..bfb58f11 100644 --- a/common/kernel/arch_pybindings_shared.h +++ b/common/kernel/arch_pybindings_shared.h @@ -145,3 +145,9 @@ fn_wrapper_1a, conv_from_str, conv_from_str>::def_wrap(ctx_cls, "isValidBelForCellType"); + +fn_wrapper_1a, + pass_through>::def_wrap(ctx_cls, "getDelayFromNS"); + +fn_wrapper_1a, + pass_through>::def_wrap(ctx_cls, "getDelayNS"); \ No newline at end of file diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc index 6d3d981c..e0a2f0f2 100644 --- a/generic/arch_pybindings.cc +++ b/generic/arch_pybindings.cc @@ -46,6 +46,13 @@ void arch_wrap_python(py::module &m) typedef linear_range WireRange; typedef linear_range AllPipRange; + typedef const std::vector &UphillPipRange; + typedef const std::vector &DownhillPipRange; + + typedef const std::vector &BelBucketRange; + typedef const std::vector &BelRangeForBelBucket; + typedef const std::vector &BelPinRange; + auto arch_cls = py::class_(m, "Arch").def(py::init()); auto dxy_cls = py::class_>(m, "DecalXY_"); @@ -62,82 +69,8 @@ void arch_wrap_python(py::module &m) .def("place", &Context::place) .def("route", &Context::route); - py::class_(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin); - - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBelType"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "checkBelAvail"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBelChecksum"); - fn_wrapper_3a_v, - addr_and_unwrap, pass_through>::def_wrap(ctx_cls, "bindBel"); - fn_wrapper_1a_v>::def_wrap( - ctx_cls, "unbindBel"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBoundBelCell"); - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getConflictingBelCell"); - fn_wrapper_0a>::def_wrap(ctx_cls, - "getBels"); - - fn_wrapper_2a, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getBelPinWire"); - fn_wrapper_1a &>, conv_from_str>::def_wrap(ctx_cls, - "getWireBelPins"); - - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getWireChecksum"); - fn_wrapper_3a_v, - addr_and_unwrap, pass_through>::def_wrap(ctx_cls, "bindWire"); - fn_wrapper_1a_v>::def_wrap( - ctx_cls, "unbindWire"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "checkWireAvail"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBoundWireNet"); - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getConflictingWireNet"); - - fn_wrapper_0a>::def_wrap( - ctx_cls, "getWires"); - - fn_wrapper_0a>::def_wrap( - ctx_cls, "getPips"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getPipChecksum"); - fn_wrapper_3a_v, - addr_and_unwrap, pass_through>::def_wrap(ctx_cls, "bindPip"); - fn_wrapper_1a_v>::def_wrap( - ctx_cls, "unbindPip"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "checkPipAvail"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBoundPipNet"); - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getConflictingPipNet"); - - fn_wrapper_1a &>, conv_from_str>::def_wrap(ctx_cls, - "getPipsDownhill"); - fn_wrapper_1a &>, conv_from_str>::def_wrap(ctx_cls, "getPipsUphill"); - - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getPipSrcWire"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getPipDstWire"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getPipDelay"); - - fn_wrapper_1a, - pass_through>::def_wrap(ctx_cls, "getDelayFromNS"); - - fn_wrapper_0a>::def_wrap( - ctx_cls, "getChipName"); - fn_wrapper_0a>::def_wrap(ctx_cls, - "archId"); + auto belpin_cls = + py::class_(m, "BelPin").def_readwrite("bel", &BelPin::bel).def_readwrite("pin", &BelPin::pin); fn_wrapper_3a, conv_from_str, pass_through, pass_through>::def_wrap(ctx_cls, "DecalXY"); @@ -145,14 +78,10 @@ void arch_wrap_python(py::module &m) typedef dict> CellMap; typedef dict> NetMap; typedef dict HierarchyMap; + typedef dict AliasMap; + typedef dict HierarchyMap; - readonly_wrapper>::def_wrap(ctx_cls, - "cells"); - readonly_wrapper>::def_wrap(ctx_cls, - "nets"); - - fn_wrapper_2a_v, - pass_through>::def_wrap(ctx_cls, "addClock"); +#include "arch_pybindings_shared.h" // Generic arch construction API fn_wrapper_4a_v, @@ -236,28 +165,6 @@ void arch_wrap_python(py::module &m) conv_from_str>::def_wrap(ctx_cls, "addCellBelPinMapping", "cell"_a, "cell_pin"_a, "bel_pin"_a); - // const\_range\ getBelBuckets() const - fn_wrapper_0a &>>::def_wrap(ctx_cls, "getBelBuckets"); - - // BelBucketId getBelBucketForBel(BelId bel) const - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelBucketForBel"); - - // BelBucketId getBelBucketForCellType(IdString cell\_type) const - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelBucketForCellType"); - - // const\_range\ getBelsInBucket(BelBucketId bucket) const - fn_wrapper_1a &>, conv_from_str>::def_wrap(ctx_cls, - "getBelsInBucket"); - - // bool isValidBelForCellType(IdString cell\_type, BelId bel) const - fn_wrapper_2a, conv_from_str, conv_from_str>::def_wrap(ctx_cls, - "isValidBelForCellType"); - WRAP_RANGE(m, Bel, conv_to_str); WRAP_RANGE(m, Wire, conv_to_str); WRAP_RANGE(m, AllPip, conv_to_str);