gowin: add support for all DFF types

Himbaechel-gowin has learned how to place DFFs of all types by tracking
the compatibility of CLK, CE and LSR inputs, as well as placing mutually
compatible flip-flops in adjacent slices.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

himbaechel/uarch/gowin/gowin.cc

@@ -45,14 +45,13 @@ void GowinImpl::pack() {
 	mod_lut_inputs();
 
 	// Constrain directly connected LUTs and FFs together to use dedicated resources
-	int lutffs = h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+	int lutffs = h.constrain_cell_pairs(
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+			pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+			pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFF, id_D}}, 1);
+			  {id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT4, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+			  {id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT3, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+			  {id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT2, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
+			  {id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},1);
-	lutffs += h.constrain_cell_pairs(pool<CellTypePort>{{id_LUT1, id_F}}, pool<CellTypePort>{{id_DFFR, id_D}}, 1);
 	log_info("Constrained %d LUTFF pairs.\n", lutffs);
 }
 
@@ -70,9 +69,12 @@ IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const {
 	if (cell_type.in(id_IBUF, id_OBUF)) {
 		return id_IOB;
 	}
-	if (cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+	if (type_is_lut(cell_type)) {
 		return id_LUT4;
 	}
+	if (type_is_dff(cell_type)) {
+		return id_DFF;
+	}
 	if (cell_type == id_GOWIN_GND) {
 		return id_GND;
 	}
@@ -88,10 +90,10 @@ bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const {
 		return cell_type.in(id_IBUF, id_OBUF);
 	}
 	if (bel_type == id_LUT4) {
-		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+		return type_is_lut(cell_type);
 	}
 	if (bel_type == id_DFF) {
-		return cell_type.in(id_DFF, id_DFFR);
+		return type_is_dff(cell_type);
 	}
 	if (bel_type == id_GND) {
 		return cell_type == id_GOWIN_GND;
@@ -107,10 +109,18 @@ void GowinImpl::assign_cell_info() {
 	for (auto &cell : ctx->cells) {
 		CellInfo *ci = cell.second.get();
 		auto &fc = fast_cell_info.at(ci->flat_index);
-		if (ci->type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4)) {
+		if (is_lut(ci)) {
 			fc.lut_f = ci->getPort(id_F);
-		} else if (ci->type.in(id_DFF, id_DFFR)) {
+		} else if (is_dff(ci)) {
 			fc.ff_d = ci->getPort(id_D);
+			fc.ff_clk = ci->getPort(id_CLK);
+			fc.ff_ce = ci->getPort(id_CE);
+			for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
+				fc.ff_lsr = ci->getPort(port);
+				if (fc.ff_lsr != nullptr) {
+					break;
+				}
+			}
 		}
 	}
 }
@@ -118,12 +128,48 @@ void GowinImpl::assign_cell_info() {
 bool GowinImpl::slice_valid(int x, int y, int z) const {
 	const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
 	const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
-	if (!lut || !ff)
+	if (!ff) {
-		return true; // always valid if only LUT or FF used
+		return true; // always valid if only LUT used
-	const auto &lut_data = fast_cell_info.at(lut->flat_index);
+	}
 	const auto &ff_data = fast_cell_info.at(ff->flat_index);
-	if (ff_data.ff_d == lut_data.lut_f)
+	if (lut) {
+		const auto &lut_data = fast_cell_info.at(lut->flat_index);
+		if (ff_data.ff_d != lut_data.lut_f)
+			return false;
+	}
+	int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
+	const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
+	if (adj_ff == nullptr) {
 		return true;
+	}
+	// DFFs must be same type or compatible
+	if (ff->type != adj_ff->type &&
+			(   (ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR))
+			 || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS))
+			 || (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE))
+			 || (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE))
+			 || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC))
+			 || (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP))
+			 || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE))
+			 || (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE))
+			 || (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR))
+			 || (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS))
+			 || (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE))
+			 || (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE))
+			 || (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC))
+			 || (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP))
+			 || (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE))
+			 || (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE))
+			 )) {
+		return false;
+	}
+
+	// CE, LSR and CLK must match
+	const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
+	if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
+		return true;
+	}
+	//
 	return false;
 }
 
@@ -140,7 +186,7 @@ void GowinImpl::mod_lut_inputs(void) {
 			if (ctx->verbose)
 				log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
 
-			if (is_lut(ctx, uc) && (user.port.str(ctx).at(0) == 'I')) {
+			if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
 				auto it_param = uc->params.find(id_INIT);
 				if (it_param == uc->params.end())
 					log_error("No initialization for lut found.\n");
@@ -185,18 +231,6 @@ void GowinImpl::mod_lut_inputs(void) {
 	}
 }
 
-// Return true if a cell is a LUT
-bool GowinImpl::is_lut(const BaseCtx *ctx, const CellInfo *cell) const {
-	switch (cell->type.index) {
-	case ID_LUT1:
-	case ID_LUT2:
-	case ID_LUT3:
-	case ID_LUT4:
-		return true;
-	default:
-		return false;
-	}
-}
 
 
 NEXTPNR_NAMESPACE_END

himbaechel/uarch/gowin/gowin.h

@@ -35,7 +35,8 @@ struct GowinImpl : HimbaechelAPI
     // Validity checking
     struct GowinCellInfo
     {
-        const NetInfo *lut_f = nullptr, *ff_d = nullptr;
+        const NetInfo *lut_f = nullptr;
+		const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
     };
     std::vector<GowinCellInfo> fast_cell_info;
     void assign_cell_info();
@@ -45,7 +46,23 @@ struct GowinImpl : HimbaechelAPI
 	void mod_lut_inputs(void);
 
 	// Return true if a cell is a LUT
-	bool is_lut(const BaseCtx *ctx, const CellInfo *cell) const;
+	inline bool type_is_lut(IdString cell_type) const {
+		return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
+	}
+	inline bool is_lut(const CellInfo *cell) const {
+		return type_is_lut(cell->type);
+	}
+	// Return true if a cell is a DFF
+	inline bool type_is_dff(IdString cell_type) const {
+		return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE,
+				     id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE,
+					 id_DFFR, id_DFFRE, id_DFFNR, id_DFFNRE,
+					 id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE,
+					 id_DFFC, id_DFFCE, id_DFFNC, id_DFFNCE);
+	}
+	inline bool is_dff(const CellInfo *cell) const {
+		return type_is_dff(cell->type);
+	}
 };
 
 struct GowinArch : HimbaechelArch

himbaechel/uarch/gowin/gowin_arch_gen.py

@@ -140,9 +140,9 @@ def create_io_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     create_switch_matrix(tt, db, x, y)
     return ttyp
 
-# XXX 6 lut+dff only for now
+# XXX lut+dff only for now
 def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
-    N = 6
+    N = 8
     lut_inputs = ['A', 'B', 'C', 'D']
     if ttyp in created_tiletypes:
         return ttyp
@@ -161,6 +161,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
     for j in range(3):
         tt.create_wire(f"CLK{j}", "TILE_CLK")
         tt.create_wire(f"LSR{j}", "TILE_LSR")
+        tt.create_wire(f"CE{j}",  "TILE_CE")
 
     # create logic cells
     for i in range(N):
@@ -169,6 +170,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
         for j, inp_name in enumerate(lut_inputs):
             tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
         tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
+        if i < 6:
             # FF data can come from LUT output, but we pretend that we can use
             # any LUT input
             tt.create_pip(f"F{i}", f"XD{i}")
@@ -179,7 +181,11 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int):
             tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
             tt.add_bel_pin(ff, "CLK", f"CLK{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "Q", f"Q{i}", PinType.OUTPUT)
+            tt.add_bel_pin(ff, "SET", f"LSR{i // 2}", PinType.INPUT)
             tt.add_bel_pin(ff, "RESET", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "PRESET", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "CLEAR", f"LSR{i // 2}", PinType.INPUT)
+            tt.add_bel_pin(ff, "CE", f"CE{i // 2}", PinType.INPUT)
     create_switch_matrix(tt, db, x, y)
     return ttyp