Merge pull request #842 from yrabbit/delays
gowin: Replace the zero delays with reasonable values.
This commit is contained in:
commit
e546cd00de
@ -371,6 +371,8 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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case ID_X06:
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case ID_X07:
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case ID_X08:
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case ID_I0:
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case ID_I1:
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len = id_X0;
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break;
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case ID_N100:
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@ -393,6 +395,7 @@ DelayQuad Arch::getWireTypeDelay(IdString wire)
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case ID_SN20:
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case ID_EW10:
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case ID_EW20:
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case ID_I01:
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len = id_FX1;
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break;
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case ID_N200:
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@ -589,8 +592,7 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
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IdString belname, bel_id;
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char buf[40];
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int z;
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// XXX do real delay
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DelayQuad delay = DelayQuad(0);
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// make all wide luts with these parameters
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struct
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{
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@ -632,26 +634,27 @@ void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
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IdString wire_i1_name = wireToGlobal(row, col, db, id_wire_i1);
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addWire(wire_i1_name, id_wire_i1, col, row);
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// dummy right pip
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DelayQuad delay = getWireTypeDelay(id_I0);
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snprintf(buf, 40, "%sF%c", mux_names[j].in_prefix, mux_names[j].in_idx[1]);
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IdString id_src_F = id(buf);
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IdString src_F = wireToGlobal(row, col, db, id_src_F);
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snprintf(buf, 40, "R%dC%d_%s__%s", grow, gcol, id_src_F.c_str(this), id_wire_i1.c_str(this));
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addPip(id(buf), id_wire_i1, src_F, wire_i1_name, delay, Loc(col, row, 0));
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// dummy left pip
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snprintf(buf, 40, "%sF%c", mux_names[j].in_prefix, mux_names[j].in_idx[0]);
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IdString id_src_F = id(buf);
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id_src_F = id(buf);
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// LUT8's I0 is wired to the right cell
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IdString src_F;
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int src_col = col;
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if (j == 7) {
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++src_col;
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delay = getWireTypeDelay(id_I01);
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}
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src_F = wireToGlobal(row, src_col, db, id_src_F);
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snprintf(buf, 40, "R%dC%d_%s__%s", grow, gcol, id_src_F.c_str(this), id_wire_i0.c_str(this));
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addPip(id(buf), id_wire_i0, src_F, wire_i0_name, delay, Loc(col, row, 0));
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// dummy right pip
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snprintf(buf, 40, "%sF%c", mux_names[j].in_prefix, mux_names[j].in_idx[1]);
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id_src_F = id(buf);
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src_F = wireToGlobal(row, col, db, id_src_F);
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snprintf(buf, 40, "R%dC%d_%s__%s", grow, gcol, id_src_F.c_str(this), id_wire_i1.c_str(this));
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addPip(id(buf), id_wire_i1, src_F, wire_i1_name, delay, Loc(col, row, 0));
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// the MUX ports
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snprintf(buf, 40, "R%dC%d_OF%d", grow, gcol, j);
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addBelOutput(belname, id_OF, id(buf));
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@ -1307,8 +1310,10 @@ void Arch::assignArchInfo()
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for (auto &cell : getCtx()->cells) {
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IdString cname = cell.first;
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CellInfo *ci = cell.second.get();
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DelayQuad delay = DelayQuad(0);
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ci->is_slice = false;
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if (ci->type == id("SLICE")) {
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switch (ci->type.index) {
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case ID_SLICE: {
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ci->is_slice = true;
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ci->ff_used = ci->params.at(id_FF_USED).as_bool();
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ci->ff_type = id(ci->params.at(id_FF_TYPE).as_string());
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@ -1333,6 +1338,24 @@ void Arch::assignArchInfo()
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DelayQuad delay = delayLookup(speed->lut.timings.get(), speed->lut.num_timings, port_delay[i]);
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addCellTimingDelay(cname, ports[i], id_F, delay);
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}
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break;
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}
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case ID_GW_MUX2_LUT8:
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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/* FALLTHRU */
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case ID_GW_MUX2_LUT7:
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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/* FALLTHRU */
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case ID_GW_MUX2_LUT6:
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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/* FALLTHRU */
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case ID_GW_MUX2_LUT5: {
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delay = delay + delayLookup(speed->lut.timings.get(), speed->lut.num_timings, id_fx_ofx1);
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addCellTimingDelay(cname, id_I0, id_OF, delay);
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addCellTimingDelay(cname, id_I1, id_OF, delay);
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}
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default:
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break;
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}
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}
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}
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@ -60,6 +60,8 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
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add_port(ctx, new_cell.get(), id_LSR, PORT_IN);
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} else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
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type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
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add_port(ctx, new_cell.get(), id_I0, PORT_IN);
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add_port(ctx, new_cell.get(), id_I1, PORT_IN);
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add_port(ctx, new_cell.get(), id_SEL, PORT_IN);
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add_port(ctx, new_cell.get(), id_OF, PORT_OUT);
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} else if (type == id_IOB) {
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@ -440,3 +440,6 @@ X(a_f)
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X(b_f)
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X(c_f)
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X(d_f)
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X(fx_ofx1)
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X(I01)
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