machxo2: Add VHDL primitives, demo, and script.

machxo2/examples/README.md

@@ -20,6 +20,7 @@ This directory contains a simple example of running `nextpnr-machxo2`:
 * `demo.sh` creates bitstreams for [TinyFPGA Ax](https://tinyfpga.com/a-series-guide.html)
   and writes the resulting bitstream to MachXO2's internal flash using
   [`tinyproga`](https://github.com/tinyfpga/TinyFPGA-A-Programmer).
+  `demo-vhdl.sh` does the same, except using the [GHDL Yosys Plugin](https://github.com/ghdl/ghdl-yosys-plugin).
 
 As `nextpnr-machxo2` is developed the contents `simple.sh`, `simtest.sh`,
 `mitertest.sh`, and `demo.sh` are subject to change.

machxo2/examples/demo-vhdl.sh

@@ -0,0 +1,24 @@
+#!/bin/sh
+
+if [ $# -lt 1 ]; then
+    echo "Usage: $0 prefix"
+    exit -1
+fi
+
+if ! grep -q "LOC" $1.vhd; then
+    echo "$1.vhd does not have LOC constraints for tinyfpga_a."
+    exit -2
+fi
+
+if [ ! -z ${TRELLIS_DB+x} ]; then
+    DB_ARG="--db $TRELLIS_DB"
+fi
+
+set -ex
+
+${YOSYS:-yosys} -p "ghdl --std=08 prims.vhd ${1}.vhd -e;
+                    attrmap -tocase LOC
+                    synth_machxo2 -json ${1}-vhdl.json"
+${NEXTPNR:-../../nextpnr-machxo2} --1200 --package QFN32 --no-iobs --json $1-vhdl.json --textcfg $1-vhdl.txt
+ecppack --compress $DB_ARG $1-vhdl.txt $1-vhdl.bit
+tinyproga -b $1-vhdl.bit

machxo2/examples/prims.vhd

@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- We don't have VHDL primitives yet, so declare them in examples for now.
+package components is
+
+component OSCH
+  generic (
+    NOM_FREQ : string := "2.08"
+  );
+  port(
+    STDBY : in std_logic;
+    OSC : out std_logic;
+    SEDSTDBY : out std_logic
+  );
+end component;
+
+end components;

machxo2/examples/tinyfpga.vhd

@@ -0,0 +1,38 @@
+library ieee ;
+context ieee.ieee_std_context;
+
+use work.components.all;
+
+entity top is
+  port (
+    pin1: out std_logic
+  );
+
+  attribute LOC: string;
+  attribute LOC of pin1: signal is "13";
+end;
+
+architecture arch of top is
+  signal clk: std_logic;
+  signal led_timer: unsigned(23 downto 0) := (others=>'0');
+begin
+
+  internal_oscillator_inst: OSCH
+  generic map (
+    NOM_FREQ => "16.63"
+  )
+  port map (
+    STDBY => '0',
+    OSC => clk
+  );
+
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      led_timer <= led_timer + 1;
+    end if;
+  end process;
+
+  pin1 <= led_timer(led_timer'left);
+
+end;