Add Context::archcheck() and "nextpnr-ice40 --test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf
parent
90fe002a36
commit
e647604e2a
146
common/archcheck.cc
Normal file
146
common/archcheck.cc
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@ -0,0 +1,146 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "nextpnr.h"
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#include "log.h"
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#if 0
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#define dbg(...) log(__VA_ARGS__)
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#else
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#define dbg(...)
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#endif
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USING_NEXTPNR_NAMESPACE
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namespace {
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void archcheck_names(const Context *ctx)
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{
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log_info("Checking entity names.\n");
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log_info("Checking bel names..\n");
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for (BelId bel : ctx->getBels()) {
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IdString name = ctx->getBelName(bel);
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BelId bel2 = ctx->getBelByName(name);
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log_assert(bel == bel2);
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}
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log_info("Checking wire names..\n");
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for (WireId wire : ctx->getWires()) {
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IdString name = ctx->getWireName(wire);
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WireId wire2 = ctx->getWireByName(name);
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log_assert(wire == wire2);
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}
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log_info("Checking pip names..\n");
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for (PipId pip : ctx->getPips()) {
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IdString name = ctx->getPipName(pip);
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PipId pip2 = ctx->getPipByName(name);
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log_assert(pip == pip2);
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}
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log_break();
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}
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void archcheck_locs(const Context *ctx)
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{
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log_info("Checking location data.\n");
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log_info("Checking all bels..\n");
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for (BelId bel : ctx->getBels()) {
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log_assert(bel != BelId());
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dbg("> %s\n", ctx->getBelName(bel).c_str(ctx));
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Loc loc = ctx->getBelLocation(bel);
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dbg(" ... %d %d %d\n", loc.x, loc.y, loc.z);
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log_assert(0 <= loc.x);
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log_assert(0 <= loc.y);
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log_assert(0 <= loc.z);
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log_assert(loc.x < ctx->getGridDimX());
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log_assert(loc.y < ctx->getGridDimY());
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log_assert(loc.z < ctx->getTileDimZ(loc.x, loc.y));
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BelId bel2 = ctx->getBelByLocation(loc);
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dbg(" ... %s\n", ctx->getBelName(bel2).c_str(ctx));
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log_assert(bel == bel2);
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}
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log_info("Checking all locations..\n");
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for (int x = 0; x < ctx->getGridDimX(); x++)
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for (int y = 0; y < ctx->getGridDimY(); y++)
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{
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dbg("> %d %d\n", x, y);
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std::unordered_set<int> usedz;
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for (int z = 0; z < ctx->getTileDimZ(x, y); z++) {
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BelId bel = ctx->getBelByLocation(Loc(x, y, z));
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if (bel == BelId())
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continue;
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Loc loc = ctx->getBelLocation(bel);
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dbg(" + %d %s\n", z, ctx->getBelName(bel).c_str(ctx));
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log_assert(x == loc.x);
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log_assert(y == loc.y);
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log_assert(z == loc.z);
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usedz.insert(z);
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}
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for (BelId bel : ctx->getBelsByTile(x, y)) {
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Loc loc = ctx->getBelLocation(bel);
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dbg(" - %d %s\n", loc.z, ctx->getBelName(bel).c_str(ctx));
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log_assert(x == loc.x);
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log_assert(y == loc.y);
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log_assert(usedz.count(loc.z));
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usedz.erase(loc.z);
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}
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log_assert(usedz.empty());
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}
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log_break();
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}
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void archcheck_conn(const Context *ctx)
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{
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#if 0
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log_info("Checking connectivity data.\n");
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log_info("Checking all wires..\n");
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for (WireId wire : ctx->getWires())
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{
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...
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}
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#endif
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}
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} // namespace
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NEXTPNR_NAMESPACE_BEGIN
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void Context::archcheck() const
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{
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log_info("Running architecture database integrity check.\n");
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log_break();
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archcheck_names(this);
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archcheck_locs(this);
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archcheck_conn(this);
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}
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NEXTPNR_NAMESPACE_END
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@ -69,17 +69,13 @@ NPNR_NORETURN void log_cmd_error(const char *format, ...) NPNR_ATTRIBUTE(format(
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void log_break();
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void log_flush();
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#ifndef NDEBUG
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static inline void log_assert_worker(bool cond, const char *expr, const char *file, int line)
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{
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if (!cond)
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log_error("Assert `%s' failed in %s:%d.\n", expr, file, line);
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}
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#define log_assert(_assert_expr_) \
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YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
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#else
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#define log_assert(_assert_expr_)
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#endif
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NEXTPNR_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
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#define log_abort() log_error("Abort in %s:%d.\n", __FILE__, __LINE__)
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#define log_ping() log("-- %s:%d %s --\n", __FILE__, __LINE__, __PRETTY_FUNCTION__)
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@ -472,6 +472,7 @@ struct Context : Arch, DeterministicRNG
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uint32_t checksum() const;
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void check() const;
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void archcheck() const;
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};
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NEXTPNR_NAMESPACE_END
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@ -373,8 +373,12 @@ with open(args.filename, "r") as f:
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if line[0] == ".extra_cell":
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if len(line) >= 5:
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mode = ("extra_cell", (line[4], int(line[1]), int(line[2]), int(line[3])))
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else:
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elif line[3] == "WARMBOOT":
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mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 0))
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elif line[3] == "PLL":
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mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 3))
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else:
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assert 0
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extra_cells[mode[1]] = []
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continue
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@ -564,11 +568,14 @@ def add_bel_ram(x, y):
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add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE")
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add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE")
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def add_bel_gb(x, y, g):
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def add_bel_gb(xy, x, y, g):
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if xy[0] != x or xy[1] != y:
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return
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bel = len(bel_name)
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bel_name.append("X%d/Y%d/gb" % (x, y))
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bel_type.append("SB_GB")
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bel_pos.append((x, y, 0))
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bel_pos.append((x, y, 2))
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bel_wires.append(list())
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add_bel_input(bel, wire_names[(x, y, "fabout")], "USER_SIGNAL_TO_GLOBAL_BUFFER")
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@ -605,51 +612,58 @@ for tile_xy, tile_type in sorted(tiles.items()):
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if tile_type == "logic":
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for i in range(8):
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add_bel_lc(tile_xy[0], tile_xy[1], i)
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if tile_type == "io":
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for i in range(2):
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add_bel_io(tile_xy[0], tile_xy[1], i)
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if dev_name == "1k":
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add_bel_gb(tile_xy, 7, 0, 0)
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add_bel_gb(tile_xy, 7, 17, 1)
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add_bel_gb(tile_xy, 13, 9, 2)
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add_bel_gb(tile_xy, 0, 9, 3)
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add_bel_gb(tile_xy, 6, 17, 4)
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add_bel_gb(tile_xy, 6, 0, 5)
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add_bel_gb(tile_xy, 0, 8, 6)
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add_bel_gb(tile_xy, 13, 8, 7)
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elif dev_name == "5k":
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add_bel_gb(tile_xy, 13, 0, 0)
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add_bel_gb(tile_xy, 13, 31, 1)
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add_bel_gb(tile_xy, 19, 31, 2)
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add_bel_gb(tile_xy, 6, 31, 3)
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add_bel_gb(tile_xy, 12, 31, 4)
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add_bel_gb(tile_xy, 12, 0, 5)
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add_bel_gb(tile_xy, 6, 0, 6)
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add_bel_gb(tile_xy, 19, 0, 7)
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elif dev_name == "8k":
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add_bel_gb(tile_xy, 33, 16, 7)
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add_bel_gb(tile_xy, 0, 16, 6)
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add_bel_gb(tile_xy, 17, 33, 1)
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add_bel_gb(tile_xy, 17, 0, 0)
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add_bel_gb(tile_xy, 0, 17, 3)
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add_bel_gb(tile_xy, 33, 17, 2)
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add_bel_gb(tile_xy, 16, 0, 5)
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add_bel_gb(tile_xy, 16, 33, 4)
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elif dev_name == "384":
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add_bel_gb(tile_xy, 7, 4, 7)
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add_bel_gb(tile_xy, 0, 4, 6)
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add_bel_gb(tile_xy, 4, 9, 1)
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add_bel_gb(tile_xy, 4, 0, 0)
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add_bel_gb(tile_xy, 0, 5, 3)
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add_bel_gb(tile_xy, 7, 5, 2)
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add_bel_gb(tile_xy, 3, 0, 5)
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add_bel_gb(tile_xy, 3, 9, 4)
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if tile_type == "ramb":
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add_bel_ram(tile_xy[0], tile_xy[1])
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if dev_name == "1k":
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add_bel_gb( 7, 0, 0)
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add_bel_gb( 7, 17, 1)
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add_bel_gb(13, 9, 2)
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add_bel_gb( 0, 9, 3)
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add_bel_gb( 6, 17, 4)
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add_bel_gb( 6, 0, 5)
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add_bel_gb( 0, 8, 6)
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add_bel_gb(13, 8, 7)
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elif dev_name == "5k":
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add_bel_gb(13, 0, 0)
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add_bel_gb(13, 31, 1)
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add_bel_gb(19, 31, 2)
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add_bel_gb( 6, 31, 3)
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add_bel_gb(12, 31, 4)
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add_bel_gb(12, 0, 5)
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add_bel_gb( 6, 0, 6)
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add_bel_gb(19, 0, 7)
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elif dev_name == "8k":
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add_bel_gb(33, 16, 7)
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add_bel_gb( 0, 16, 6)
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add_bel_gb(17, 33, 1)
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add_bel_gb(17, 0, 0)
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add_bel_gb( 0, 17, 3)
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add_bel_gb(33, 17, 2)
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add_bel_gb(16, 0, 5)
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add_bel_gb(16, 33, 4)
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elif dev_name == "384":
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add_bel_gb( 7, 4, 7)
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add_bel_gb( 0, 4, 6)
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add_bel_gb( 4, 9, 1)
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add_bel_gb( 4, 0, 0)
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add_bel_gb( 0, 5, 3)
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add_bel_gb( 7, 5, 2)
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add_bel_gb( 3, 0, 5)
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add_bel_gb( 3, 9, 4)
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for ec in sorted(extra_cells.keys()):
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if ec[1] == tile_xy[0] and ec[2] == tile_xy[1]:
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add_bel_ec(ec)
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for ec in sorted(extra_cells.keys()):
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add_bel_ec(ec)
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if ec[1] == 0 and ec[2] == 0:
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add_bel_ec(ec)
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class BinaryBlobAssembler:
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def __init__(self, cname, endianness, nodebug = False):
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@ -107,6 +107,7 @@ int main(int argc, char *argv[])
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options.add_options()("seed", po::value<int>(), "seed value for random number generator");
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options.add_options()("version,V", "show version");
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options.add_options()("tmfuzz", "run path delay estimate fuzzer");
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options.add_options()("test", "check architecture database integrity");
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#ifdef ICE40_HX1K_ONLY
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options.add_options()("hx1k", "set device type to iCE40HX1K");
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#else
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@ -315,6 +316,9 @@ int main(int argc, char *argv[])
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std::cout << "</svg>\n";
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}
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if (vm.count("test"))
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ctx->archcheck();
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if (vm.count("tmfuzz")) {
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std::vector<WireId> src_wires, dst_wires;
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@ -360,8 +364,10 @@ int main(int argc, char *argv[])
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ctx->chip_info->wire_data[dst.index].type);
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}
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}
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if (vm.count("freq"))
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ctx->target_freq = vm["freq"].as<double>() * 1e6;
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ctx->timing_driven = true;
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if (vm.count("no-tmdriv"))
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ctx->timing_driven = false;
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