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mistral: Debugging carry chain issues

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-13 23:46:08 +01:00
parent 3313d5267a
commit e688ee0e89
2 changed files with 34 additions and 13 deletions
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29
mistral/lab.cc
View File

@ -42,20 +42,20 @@ static void create_alm(Arch *arch, int x, int y, int z, uint32_t lab_idx)
WireId carry_in, share_in; WireId carry_in, share_in;
WireId carry_out, share_out; WireId carry_out, share_out;
if (z == 0 && i == 0) { if (z == 0 && i == 0) {
if (y == arch->getGridDimY() - 1) { carry_in = arch->add_wire(x, y, id_CI);
// Base case share_in = arch->add_wire(x, y, id_SHAREIN);
carry_in = arch->add_wire(x, y, id_CARRY_START); if (y < (arch->getGridDimY() - 1)) {
share_in = arch->add_wire(x, y, id_CARRY_START); // Carry is split at tile boundary (TTO_DIS bit), add a PIP to represent this.
} else { // TODO: what about BTO_DIS, in the middle of the LAB?
// Output of last tile arch->add_pip(arch->add_wire(x, y + 1, id_CO), carry_in);
carry_in = arch->add_wire(x, y + 1, id_CO); arch->add_pip(arch->add_wire(x, y + 1, id_SHAREOUT), share_in);
share_in = arch->add_wire(x, y + 1, id_SHAREOUT);
} }
} else { } else {
// Output from last combinational unit // Output from last combinational unit
carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1))); carry_in = arch->add_wire(x, y, arch->id(stringf("CARRY[%d]", (z * 2 + i) - 1)));
share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1))); share_in = arch->add_wire(x, y, arch->id(stringf("SHARE[%d]", (z * 2 + i) - 1)));
} }
if (z == 9 && i == 1) { if (z == 9 && i == 1) {
carry_out = arch->add_wire(x, y, id_CO); carry_out = arch->add_wire(x, y, id_CO);
share_out = arch->add_wire(x, y, id_SHAREOUT); share_out = arch->add_wire(x, y, id_SHAREOUT);
@ -582,7 +582,7 @@ static void assign_lut6_inputs(CellInfo *cell, int lut)
if (!cell->ports.count(log) || cell->ports.at(log).net == nullptr) if (!cell->ports.count(log) || cell->ports.at(log).net == nullptr)
continue; continue;
cell->pin_data[log].bel_pins.clear(); cell->pin_data[log].bel_pins.clear();
cell->pin_data[log].bel_pins.push_back(phys_pins.at(++phys_idx)); cell->pin_data[log].bel_pins.push_back(phys_pins.at(phys_idx++));
} }
} }
} // namespace } // namespace
@ -640,16 +640,19 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm)
continue; continue;
// Work out which physical ports are available // Work out which physical ports are available
std::vector<IdString> avail_phys_ports; std::vector<IdString> avail_phys_ports;
// D/C always available and dedicated to the half, in L5 mode
avail_phys_ports.push_back((i == 1) ? id_D : id_C); avail_phys_ports.push_back((i == 1) ? id_D : id_C);
if (b_avail)
avail_phys_ports.push_back(id_B);
if (a_avail)
avail_phys_ports.push_back(id_A);
// In arithmetic mode, Ei can only be used for D0 and Fi can only be used for D1 // In arithmetic mode, Ei can only be used for D0 and Fi can only be used for D1
// otherwise, these are general and dedicated to one half
if (!luts[i]->combInfo.is_carry) { if (!luts[i]->combInfo.is_carry) {
avail_phys_ports.push_back((i == 1) ? id_E1 : id_E0); avail_phys_ports.push_back((i == 1) ? id_E1 : id_E0);
avail_phys_ports.push_back((i == 1) ? id_F1 : id_F0); avail_phys_ports.push_back((i == 1) ? id_F1 : id_F0);
} }
// A and B might be used for shared signals, or already used by the other half
if (b_avail)
avail_phys_ports.push_back(id_B);
if (a_avail)
avail_phys_ports.push_back(id_A);
int phys_idx = 0; int phys_idx = 0;
for (int j = 0; j < luts[i]->combInfo.lut_input_count; j++) { for (int j = 0; j < luts[i]->combInfo.lut_input_count; j++) {

18
mistral/pack.cc
View File

@ -312,6 +312,24 @@ struct MistralPacker
chain.at(i)->cluster = chain.at(0)->name; chain.at(i)->cluster = chain.at(0)->name;
chain.at(0)->constr_children.push_back(chain.at(i)); chain.at(0)->constr_children.push_back(chain.at(i));
} }
if (ctx->debug) {
log_info("Chain: \n");
for (int i = 0; i < int(chain.size()); i++) {
auto &c = chain.at(i);
log_info(" i=%d cell=%s dy=%d z=%d ci=%s co=%s\n", i, ctx->nameOf(c), c->constr_y, c->constr_z,
ctx->nameOf(get_net_or_empty(c, id_CI)), ctx->nameOf(get_net_or_empty(c, id_CO)));
}
}
}
// Check we reached all the cells in the above pass
for (auto cell : sorted(ctx->cells)) {
CellInfo *ci = cell.second;
if (ci->type != id_MISTRAL_ALUT_ARITH)
continue;
if (ci->cluster == ClusterId())
log_error("Failed to include arith cell '%s' in any chain (CI=%s)\n", ctx->nameOf(ci),
ctx->nameOf(get_net_or_empty(ci, id_CI)));
} }
} }