ecp5: Add missing clock edge assignments
Signed-off-by: gatecat <gatecat@ds0.me>
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@ -1067,6 +1067,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
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}
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} else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
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info.clock_port = id_CLK;
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info.edge = RISING_EDGE;
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if (cell->ports.at(port).type == PORT_OUT) {
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info.clockToQ = DelayQuad(getDelayFromNS(0.5));
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} else {
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@ -1075,6 +1076,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
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}
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} else if (cell->type == id_DQSBUFM) {
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info.clock_port = id_SCLK;
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info.edge = RISING_EDGE;
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if (port == id_DATAVALID) {
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info.clockToQ = DelayQuad(getDelayFromNS(0.2));
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} else if (port == id_READ0 || port == id_READ1) {
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