caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ecp5: Add missing clock edge assignments

Browse Source 
Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-06-10 13:10:29 +01:00
parent 13c037cc08
commit e9d5b75d1d
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ecp5/arch.cc
View File

@ -1067,6 +1067,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
} }
} else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
info.clock_port = id_CLK; info.clock_port = id_CLK;
info.edge = RISING_EDGE;
if (cell->ports.at(port).type == PORT_OUT) { if (cell->ports.at(port).type == PORT_OUT) {
info.clockToQ = DelayQuad(getDelayFromNS(0.5)); info.clockToQ = DelayQuad(getDelayFromNS(0.5));
} else { } else {
@ -1075,6 +1076,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
} }
} else if (cell->type == id_DQSBUFM) { } else if (cell->type == id_DQSBUFM) {
info.clock_port = id_SCLK; info.clock_port = id_SCLK;
info.edge = RISING_EDGE;
if (port == id_DATAVALID) { if (port == id_DATAVALID) {
info.clockToQ = DelayQuad(getDelayFromNS(0.2)); info.clockToQ = DelayQuad(getDelayFromNS(0.2));
} else if (port == id_READ0 || port == id_READ1) { } else if (port == id_READ0 || port == id_READ1) {