constraints
This commit is contained in:
parent
e14f5fccbd
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116
gowin/arch.cc
116
gowin/arch.cc
@ -19,6 +19,7 @@
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#include <iostream>
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#include <math.h>
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#include <regex>
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#include "embed.h"
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#include "nextpnr.h"
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#include "placer1.h"
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@ -300,7 +301,7 @@ IdString Arch::wireToGlobal(int &row, int &col, const DatabasePOD *db, IdString
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return id(buf);
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}
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const PairPOD* pairLookup(const PairPOD *list, const size_t len, const int dest)
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const PairPOD *pairLookup(const PairPOD *list, const size_t len, const int dest)
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{
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for (size_t i = 0; i < len; i++) {
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const PairPOD *pair = &list[i];
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@ -311,36 +312,34 @@ const PairPOD* pairLookup(const PairPOD *list, const size_t len, const int dest)
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return nullptr;
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}
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bool aliasCompare (GlobalAliasPOD i, GlobalAliasPOD j) {
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return (i.dest_row<j.dest_row) ||
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(i.dest_row==j.dest_row && i.dest_col<j.dest_col) ||
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(i.dest_row==j.dest_row && i.dest_col==j.dest_col && i.dest_id<j.dest_id);
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}
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bool timingCompare (TimingPOD i, TimingPOD j) {
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return i.name_id < j.name_id;
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}
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template <class T, class C>
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const T* genericLookup(const T *first, int len, const T val, C compare)
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bool aliasCompare(GlobalAliasPOD i, GlobalAliasPOD j)
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{
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auto res = std::lower_bound(first, first+len, val, compare);
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if (res-first != len && !compare(val, *res)) {
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return (i.dest_row < j.dest_row) || (i.dest_row == j.dest_row && i.dest_col < j.dest_col) ||
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(i.dest_row == j.dest_row && i.dest_col == j.dest_col && i.dest_id < j.dest_id);
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}
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bool timingCompare(TimingPOD i, TimingPOD j) { return i.name_id < j.name_id; }
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template <class T, class C> const T *genericLookup(const T *first, int len, const T val, C compare)
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{
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auto res = std::lower_bound(first, first + len, val, compare);
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if (res - first != len && !compare(val, *res)) {
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return res;
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} else {
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return nullptr;
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}
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}
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DelayInfo delayLookup(const TimingPOD* first, int len, IdString name) {
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DelayInfo delayLookup(const TimingPOD *first, int len, IdString name)
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{
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TimingPOD needle;
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needle.name_id = name.index;
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const TimingPOD *timing = genericLookup(first, len, needle, timingCompare);
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DelayInfo info;
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if (timing != nullptr) {
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info.maxFall = std::max(timing->ff, timing->rf)/1000;
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info.minFall = std::min(timing->ff, timing->rf)/1000;
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info.maxRaise = std::max(timing->rr, timing->fr)/1000;
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info.minRaise = std::min(timing->rr, timing->fr)/1000;
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info.maxFall = std::max(timing->ff, timing->rf) / 1000;
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info.minFall = std::min(timing->ff, timing->rf) / 1000;
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info.maxRaise = std::max(timing->rr, timing->fr) / 1000;
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info.minRaise = std::min(timing->rr, timing->fr) / 1000;
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} else {
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info.maxFall = 0;
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info.minFall = 0;
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@ -350,11 +349,11 @@ DelayInfo delayLookup(const TimingPOD* first, int len, IdString name) {
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return info;
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}
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DelayInfo Arch::getWireTypeDelay(IdString wire) {
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DelayInfo Arch::getWireTypeDelay(IdString wire)
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{
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IdString len;
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IdString glbsrc;
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switch (wire.index)
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{
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switch (wire.index) {
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case ID_X01:
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case ID_X02:
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case ID_X03:
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@ -458,7 +457,7 @@ DelayInfo Arch::getWireTypeDelay(IdString wire) {
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glbsrc = id_BRANCH_PCLK;
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break;
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default:
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if (wire.str(this).rfind("SPINE", 0) == 0){
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if (wire.str(this).rfind("SPINE", 0) == 0) {
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glbsrc = ID_CENT_SPINE_PCLK;
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} else if (wire.str(this).rfind("UNK", 0) == 0) {
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glbsrc = ID_PIO_CENT_PCLK;
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@ -479,12 +478,35 @@ DelayInfo Arch::getWireTypeDelay(IdString wire) {
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}
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}
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void Arch::read_cst(std::istream &in) {
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std::regex iobre = std::regex("IO_LOC +\"([^\"]+)\" +([^ ;]+);");
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std::smatch match;
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std::string line;
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while (!in.eof()) {
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std::getline(in, line);
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if(!std::regex_match(line, match, iobre)) continue;
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std::cout << match[1] << " " << match[2] << std::endl;
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IdString net = id(match[1]);
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IdString pinname = id(match[2]);
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const PairPOD *belname = pairLookup(package->pins.get(), package->num_pins, pinname.index);
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if ( belname == nullptr)
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log_error("Pin %s not found", pinname.c_str(this));
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//BelId bel = getBelByName(belname->src_id);
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// for (auto cell : sorted(cells)) {
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// std::cout << cell.first.str(this) << std::endl;
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// }
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auto it = cells.find(net);
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if (it == cells.end())
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log_error("Cell %s not found", net.c_str(this));
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std::string bel = IdString(belname->src_id).str(this);
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it->second->attrs[ID_BEL] = bel;
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}
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}
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Arch::Arch(ArchArgs args) : args(args)
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{
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family = args.family;
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device = args.device;
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package = args.package;
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// Load database
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std::string chipdb = stringf("gowin/chipdb-%s.bin", family.c_str());
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@ -501,9 +523,9 @@ Arch::Arch(ArchArgs args) : args(args)
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}
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// setup timing info
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speed = nullptr;
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for (unsigned int i=0; i<db->num_speeds; i++) {
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for (unsigned int i = 0; i < db->num_speeds; i++) {
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const TimingClassPOD *tc = &db->speeds[i];
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//std::cout << IdString(tc->name_id).str(this) << std::endl;
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// std::cout << IdString(tc->name_id).str(this) << std::endl;
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if (IdString(tc->name_id) == id(args.speed)) {
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speed = tc->groups.get();
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break;
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@ -512,6 +534,22 @@ Arch::Arch(ArchArgs args) : args(args)
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if (speed == nullptr) {
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log_error("Unsuported speed grade '%s'.\n", args.speed.c_str());
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}
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package = nullptr;
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for (unsigned int i = 0; i < db->num_packages; i++) {
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auto pkg = &db->packages[i];
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// std::cout << IdString(pkg->name_id).str(this) << std::endl;
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if (IdString(pkg->name_id) == id(args.package)) {
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package = pkg;
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break;
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}
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// for (int j=0; j < pkg->num_pins; j++) {
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// auto pin = pkg->pins[j];
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// std::cout << IdString(pin.src_id).str(this) << " " << IdString(pin.dest_id).str(this) << std::endl;
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// }
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}
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if (package == nullptr) {
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log_error("Unsuported package '%s'.\n", args.package.c_str());
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}
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// setup db
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char buf[32];
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for (int i = 0; i < db->rows * db->cols; i++) {
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@ -519,9 +557,9 @@ Arch::Arch(ArchArgs args) : args(args)
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int col = i % db->cols;
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const TilePOD *tile = db->grid[i].get();
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// setup wires
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const PairPOD* pips[2] = { tile->pips.get(), tile->clock_pips.get()};
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unsigned int num_pips[2] = { tile->num_pips, tile->num_clock_pips};
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for(int p = 0; p < 2; p++) {
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const PairPOD *pips[2] = {tile->pips.get(), tile->clock_pips.get()};
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unsigned int num_pips[2] = {tile->num_pips, tile->num_clock_pips};
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for (int p = 0; p < 2; p++) {
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for (unsigned int j = 0; j < num_pips[p]; j++) {
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const PairPOD pip = pips[p][j];
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int destrow = row;
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@ -644,9 +682,9 @@ Arch::Arch(ArchArgs args) : args(args)
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int row = i / db->cols;
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int col = i % db->cols;
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const TilePOD *tile = db->grid[i].get();
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const PairPOD* pips[2] = { tile->pips.get(), tile->clock_pips.get()};
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unsigned int num_pips[2] = { tile->num_pips, tile->num_clock_pips};
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for(int p = 0; p < 2; p++) {
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const PairPOD *pips[2] = {tile->pips.get(), tile->clock_pips.get()};
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unsigned int num_pips[2] = {tile->num_pips, tile->num_clock_pips};
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for (int p = 0; p < 2; p++) {
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for (unsigned int j = 0; j < num_pips[p]; j++) {
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const PairPOD pip = pips[p][j];
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int destrow = row;
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@ -659,13 +697,13 @@ Arch::Arch(ArchArgs args) : args(args)
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IdString gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
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snprintf(buf, 32, "R%dC%d_%s_%s", row + 1, col + 1, IdString(pip.src_id).c_str(this),
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IdString(pip.dest_id).c_str(this));
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IdString(pip.dest_id).c_str(this));
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IdString pipname = id(buf);
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DelayInfo delay = getWireTypeDelay(pip.dest_id);
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// local alias
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auto local_alias = pairLookup(tile->aliases.get(), tile->num_aliases, srcid.index);
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// std::cout << "srcid " << srcid.str(this) << std::endl;
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if(local_alias!=nullptr) {
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if (local_alias != nullptr) {
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srcid = local_alias->src_id;
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gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
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}
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@ -676,12 +714,12 @@ Arch::Arch(ArchArgs args) : args(args)
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alias.dest_row = srcrow;
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alias.dest_id = srcid.index;
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auto alias_src = genericLookup(db->aliases.get(), db->num_aliases, alias, aliasCompare);
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if(alias_src!=nullptr) {
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if (alias_src != nullptr) {
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srccol = alias_src->src_col;
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srcrow = alias_src->src_row;
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srcid = alias_src->src_id;
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gsrcname = wireToGlobal(srcrow, srccol, db, srcid);
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//std::cout << buf << std::endl;
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// std::cout << buf << std::endl;
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}
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addPip(pipname, pip.dest_id, gsrcname, gdestname, delay, Loc(col, row, j));
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}
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@ -1133,7 +1171,7 @@ void Arch::assignArchInfo()
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// add timing paths
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addCellTimingClock(cname, id_CLK);
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IdString ports[4] = {id_A, id_B, id_C, id_D};
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for (int i=0; i<4; i++) {
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for (int i = 0; i < 4; i++) {
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DelayInfo setup = delayLookup(speed->dff.timings.get(), speed->dff.num_timings, id_clksetpos);
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DelayInfo hold = delayLookup(speed->dff.timings.get(), speed->dff.num_timings, id_clkholdpos);
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// DelayInfo setup = getDelayFromNS(0.1);
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@ -1144,7 +1182,7 @@ void Arch::assignArchInfo()
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// DelayInfo clkout = getDelayFromNS(0.1);
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addCellTimingClockToOut(cname, id_Q, id_CLK, clkout);
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IdString port_delay[4] = {id_a_f, id_b_f, id_c_f, id_d_f};
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for (int i=0; i<4; i++) {
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for (int i = 0; i < 4; i++) {
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DelayInfo delay = delayLookup(speed->lut.timings.get(), speed->lut.num_timings, port_delay[i]);
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// DelayInfo delay = getDelayFromNS(0.1);
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addCellTimingDelay(cname, ports[i], id_F, delay);
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@ -1167,7 +1205,7 @@ bool Arch::cellsCompatible(const CellInfo **cells, int count) const
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const CellInfo *ci = cells[i];
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if (ci->is_slice && ci->slice_clk != nullptr) {
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Loc loc = getBelLocation(ci->bel);
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int cls = loc.z/2;
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int cls = loc.z / 2;
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bool ff_used = ci->params.at(id_FF_USED).as_bool();
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if (loc.z >= 6 && ff_used) // top slice have no ff
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return false;
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13
gowin/arch.h
13
gowin/arch.h
@ -118,6 +118,12 @@ NPNR_PACKED_STRUCT(struct TimingClassPOD {
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RelPtr<TimingGroupsPOD> groups;
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});
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NPNR_PACKED_STRUCT(struct PackagePOD {
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uint32_t name_id;
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uint32_t num_pins;
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RelPtr<PairPOD> pins;
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});
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NPNR_PACKED_STRUCT(struct DatabasePOD {
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RelPtr<char> family;
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uint32_t version;
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@ -128,6 +134,8 @@ NPNR_PACKED_STRUCT(struct DatabasePOD {
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RelPtr<GlobalAliasPOD> aliases;
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uint32_t num_speeds;
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RelPtr<TimingClassPOD> speeds;
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uint32_t num_packages;
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RelPtr<PackagePOD> packages;
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uint16_t num_constids;
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uint16_t num_ids;
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RelPtr<RelPtr<char>> id_strs;
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@ -141,7 +149,7 @@ struct ArchArgs
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std::string package;
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// y = mx + c relationship between distance and delay for interconnect
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// delay estimates
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double delayScale = 0.1, delayOffset = 0.4;
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double delayScale = 0.4, delayOffset = 0.4;
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};
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struct WireInfo;
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@ -229,7 +237,7 @@ struct Arch : BaseCtx
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{
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std::string family;
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std::string device;
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std::string package;
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const PackagePOD *package;
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const TimingGroupsPOD *speed;
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std::unordered_map<IdString, WireInfo> wires;
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@ -287,6 +295,7 @@ struct Arch : BaseCtx
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IdString wireToGlobal(int &row, int &col, const DatabasePOD* db, IdString &wire);
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DelayInfo getWireTypeDelay(IdString wire);
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void read_cst(std::istream &in);
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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@ -74,9 +74,6 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
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void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
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{
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for(auto f : lut->ports) {
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std::cout << f.first.str(ctx) << std::endl;
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}
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lc->params[id_INIT] = lut->params[id_INIT];
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IdString sim_names[4] = {id_I0, id_I1, id_I2, id_I3};
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@ -101,9 +98,6 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
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replace_port(dff, id_RESET, lc, id_LSR);
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replace_port(dff, id_CLEAR, lc, id_LSR);
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replace_port(dff, id_PRESET, lc, id_LSR);
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for(auto f : dff->ports) {
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std::cout << f.first.str(ctx) << std::endl;
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}
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if (pass_thru_lut) {
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// Fill LUT with alternating 10
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const int init_size = 1 << 4;
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@ -393,6 +393,7 @@ X(FF_TYPE)
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X(INPUT_USED)
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X(OUTPUT_USED)
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X(ENABLE_USED)
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X(BEL)
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// ports
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X(EN)
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@ -65,13 +65,13 @@ std::unique_ptr<Context> GowinCommandHandler::createContext(std::unordered_map<s
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void GowinCommandHandler::customAfterLoad(Context *ctx)
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{
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// if (vm.count("cst")) {
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// std::string filename = vm["pdc"].as<std::string>();
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// std::ifstream in(filename);
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// if (!in)
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// log_error("Failed to open input PDC file %s.\n", filename.c_str());
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// ctx->read_pdc(in);
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// }
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if (vm.count("cst")) {
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std::string filename = vm["cst"].as<std::string>();
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std::ifstream in(filename);
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if (!in)
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log_error("Failed to open input CST file %s.\n", filename.c_str());
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ctx->read_cst(in);
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}
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}
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int main(int argc, char *argv[])
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@ -250,11 +250,11 @@ static void pack_io(Context *ctx)
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create_generic_cell(ctx, id_IOB, ci->name.str(ctx) + "$iob");
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gwio_to_iob(ctx, ci, ice_cell.get(), packed_cells);
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new_cells.push_back(std::move(ice_cell));
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iob = new_cells.back().get();
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auto gwiob = new_cells.back().get();
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packed_cells.insert(ci->name);
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if (iob != nullptr)
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std::copy(ci->attrs.begin(), ci->attrs.end(), std::inserter(iob->attrs, iob->attrs.begin()));
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std::copy(iob->attrs.begin(), iob->attrs.end(), std::inserter(gwiob->attrs, gwiob->attrs.begin()));
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}
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}
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for (auto pcell : packed_cells) {
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