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Fix small isses and code formatting

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Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
Maciej Dudek 2021-09-27 16:16:33 +02:00
parent 439ae9609b
commit ea489f6d93
5 changed files with 150 additions and 148 deletions
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8
fpga_interchange/arch.h
View File

@ -899,10 +899,10 @@ struct Arch : ArchAPI<ArchRanges>
ArcBounds getClusterBounds(ClusterId cluster) const override;
Loc getClusterOffset(const CellInfo *cell) const override;
bool isClusterStrict(const CellInfo *cell) const override;
bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &,CellInfo*,
BelId, std::vector<std::pair<CellInfo *, BelId>> &) const;
bool macro_cluster_placement(const Context *, const Cluster &, const ClusterPOD &,CellInfo*,
BelId, std::vector<std::pair<CellInfo *, BelId>> &) const;
bool normal_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,
std::vector<std::pair<CellInfo *, BelId>> &) const;
bool macro_cluster_placement(const Context *, const Cluster &, const ClusterPOD &, CellInfo *, BelId,
std::vector<std::pair<CellInfo *, BelId>> &) const;
bool getClusterPlacement(ClusterId cluster, BelId root_bel,
std::vector<std::pair<CellInfo *, BelId>> &placement) const override;

94
fpga_interchange/arch_pack_clusters.cc
View File

@ -189,9 +189,9 @@ CellInfo *Arch::getClusterRootCell(ClusterId cluster) const
return clusters.at(cluster).root;
}
bool Arch::normal_cluster_placement(
const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
CellInfo *root_cell, BelId root_bel, std::vector<std::pair<CellInfo *, BelId>> &placement) const
bool Arch::normal_cluster_placement(const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
CellInfo *root_cell, BelId root_bel,
std::vector<std::pair<CellInfo *, BelId>> &placement) const
{
BelId next_bel;
@ -278,19 +278,18 @@ bool Arch::normal_cluster_placement(
static dict<int32_t, dict<IdString, BelId>> tileAndBelNameToBelIdCache;
BelId check_and_return(int32_t tile, IdString name){
if(tileAndBelNameToBelIdCache.count(tile)
&& tileAndBelNameToBelIdCache[tile].count(name))
BelId check_and_return(int32_t tile, IdString name)
{
if (tileAndBelNameToBelIdCache.count(tile) && tileAndBelNameToBelIdCache[tile].count(name))
return tileAndBelNameToBelIdCache[tile][name];
else
return BelId();
}
void add_to_cache(int32_t tile, IdString name, BelId t){
tileAndBelNameToBelIdCache[tile][name] = t;
}
void add_to_cache(int32_t tile, IdString name, BelId t) { tileAndBelNameToBelIdCache[tile][name] = t; }
bool find_site_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel, uint32_t &idx){
bool find_site_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel, uint32_t &idx)
{
bool found = false;
const auto &site_inst = ctx->get_site_inst(root_bel);
IdString site_type(site_inst.site_type);
@ -314,8 +313,9 @@ bool find_site_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel
return found;
}
bool find_placement_idx(const Context *ctx, const ClusterPOD &cluster,
BelId root_bel, uint32_t idx, uint32_t &placement_idx){
bool find_placement_idx(const Context *ctx, const ClusterPOD &cluster, BelId root_bel, uint32_t idx,
uint32_t &placement_idx)
{
bool found = false;
const auto &bel_data = bel_info(ctx->chip_info, root_bel);
IdString root_bel_name(bel_data.name);
@ -341,8 +341,9 @@ bool find_placement_idx(const Context *ctx, const ClusterPOD &cluster,
return found;
}
dict<uint32_t, BelId> idx_bel_mapping(const Context *ctx, BelId root_bel,
const ClusterPOD &cluster, uint32_t idx, uint32_t placement_idx){
dict<uint32_t, BelId> idx_bel_mapping(const Context *ctx, BelId root_bel, const ClusterPOD &cluster, uint32_t idx,
uint32_t placement_idx)
{
dict<uint32_t, BelId> idx_bel_map;
auto root_bel_full_name = ctx->getBelName(root_bel);
uint32_t t_idx = 0;
@ -355,7 +356,7 @@ dict<uint32_t, BelId> idx_bel_mapping(const Context *ctx, BelId root_bel,
if (t == BelId()) {
for (uint32_t j = 0; j < root_bel_full_name.size(); j++)
cpy.ids[j] = root_bel_full_name[j];
cpy.ids[1] = s_bel;
cpy.ids[root_bel_full_name.size() - 1] = s_bel;
t = ctx->getBelByName(cpy);
add_to_cache(root_bel.tile, s_bel, t);
}
@ -372,9 +373,9 @@ dict<uint32_t, BelId> idx_bel_mapping(const Context *ctx, BelId root_bel,
return idx_bel_map;
}
bool Arch::macro_cluster_placement(
const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
CellInfo *root_cell, BelId root_bel, std::vector<std::pair<CellInfo *, BelId>> &placement) const
bool Arch::macro_cluster_placement(const Context *ctx, const Cluster &packed_cluster, const ClusterPOD &cluster_data,
CellInfo *root_cell, BelId root_bel,
std::vector<std::pair<CellInfo *, BelId>> &placement) const
{
// Check root_bel site_type
const auto &cluster = cluster_info(chip_info, packed_cluster.index);
@ -409,11 +410,9 @@ bool Arch::getClusterPlacement(ClusterId cluster, BelId root_bel,
if (!ctx->isValidBelForCellType(root_cell->type, root_bel))
return false;
if (!cluster_data.from_macro)
return normal_cluster_placement(ctx, packed_cluster, cluster_data, root_cell,
root_bel, placement);
return normal_cluster_placement(ctx, packed_cluster, cluster_data, root_cell, root_bel, placement);
else {
bool temp = macro_cluster_placement(ctx, packed_cluster, cluster_data, root_cell,
root_bel, placement);
bool temp = macro_cluster_placement(ctx, packed_cluster, cluster_data, root_cell, root_bel, placement);
return temp;
}
}
@ -506,7 +505,10 @@ static bool check_cluster_cells_compatibility(CellInfo *old_cell, CellInfo *new_
return true;
}
bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &domain, Context *ctx){
bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &domain,
Context *ctx)
{
// Reduce X domain by removing values, which don't satisfy binary constraint with values from Y domain.
bool change = false;
std::vector<CellInfo *> remove_cell;
uint32_t counter = 0;
@ -520,7 +522,8 @@ bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, po
for (const auto &y_cell : domain[y]) {
found = true;
for (const auto edge : cluster->connection_graph[x].connections[counter].edges) {
if (!x_cell->ports.count(IdString(edge.cell_pin)) || !y_cell->ports.count(IdString(edge.other_cell_pin))){
if (!x_cell->ports.count(IdString(edge.cell_pin)) ||
!y_cell->ports.count(IdString(edge.other_cell_pin))) {
found = false;
break;
}
@ -533,7 +536,8 @@ bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, po
}
bool x_driver = x_net->driver.cell == x_cell;
bool y_driver = y_net->driver.cell == y_cell;
if ((edge.dir != 0 || !y_driver) && (edge.dir != 1 || !x_driver) && (edge.dir != 2 || y_driver || x_driver)){
if ((edge.dir != 0 || !y_driver) && (edge.dir != 1 || !x_driver) &&
(edge.dir != 2 || y_driver || x_driver)) {
found = false;
break;
}
@ -553,14 +557,15 @@ bool reduce(uint32_t x, uint32_t y, const ClusterPOD *cluster, dict<uint32_t, po
return change;
}
void binary_constraint_check(const ClusterPOD *cluster,
std::queue<std::pair<uint32_t, uint32_t>> &workqueue,
dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx){
void binary_constraint_check(const ClusterPOD *cluster, std::queue<std::pair<uint32_t, uint32_t>> &workqueue,
dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx)
{
while (!workqueue.empty()) {
std::pair<uint32_t, uint32_t> arc = workqueue.front();
workqueue.pop();
uint32_t x, y;
x = arc.first; y = arc.second;
x = arc.first;
y = arc.second;
if (reduce(x, y, cluster, idx_to_cells, ctx)) {
for (const auto &node : cluster->connection_graph) {
if (node.idx != arc.first)
@ -572,8 +577,8 @@ void binary_constraint_check(const ClusterPOD *cluster,
}
}
bool back_solver(const ClusterPOD *cluster,
dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx){
bool back_solver(const ClusterPOD *cluster, dict<uint32_t, pool<CellInfo *, hash_ptr_ops>> &idx_to_cells, Context *ctx)
{
dict<CellInfo *, pool<uint32_t>, hash_ptr_ops> possible_idx;
for (const auto &arc : idx_to_cells)
for (const auto &cell : arc.second)
@ -593,7 +598,8 @@ bool back_solver(const ClusterPOD *cluster,
copy_idx_to_cells[arc.first].insert(cell);
std::queue<std::pair<uint32_t, uint32_t>> workqueue;
while (!prep.empty()) {
uint32_t idx = prep.front(); prep.pop();
uint32_t idx = prep.front();
prep.pop();
for (const auto &connection : cluster->connection_graph[idx].connections)
if (arc.first != connection.target_idx)
workqueue.push(std::pair<uint32_t, uint32_t>(arc.first, connection.target_idx));
@ -631,7 +637,11 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
if (roots.count(ci->macro_parent))
continue;
// Simple check based on cell type counting
dict<IdString, uint32_t> cells_in_macro, counter;
// cells_in_macro stores cell_types used in tested cluster and
// cell_types that are in macro_to_cells[ci->macro_parent]
pool<IdString> cell_types;
for (auto &cell_type : cluster->required_cells) {
cells_in_macro[IdString(cell_type.name)] = cell_type.count;
@ -640,8 +650,6 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
for (auto &node_cell : macro_to_cells[ci->macro_parent]) {
auto cell_type = node_cell->type;
if(!counter.count(cell_type))
counter[cell_type] = 0;
counter[cell_type]++;
cell_types.insert(cell_type);
}
@ -651,7 +659,8 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
log_info("Required: %s %d\n", cell_type.c_str(ctx), cells_in_macro[cell_type]);
if (ctx->verbose && cells_in_macro.count(cell_type))
log_info("Have: %s %d\n", cell_type.c_str(ctx), counter[cell_type]);
if(!cells_in_macro.count(cell_type) || !counter.count(cell_type) || cells_in_macro[cell_type] != counter[cell_type])
if (!cells_in_macro.count(cell_type) || !counter.count(cell_type) ||
cells_in_macro[cell_type] != counter[cell_type])
failed = true;
if (failed && ctx->verbose)
log_info("Cell count stage failed, for sure not this cluster\n");
@ -669,8 +678,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
for (auto &cell : macro_to_cells[ci->macro_parent])
for (auto &node : cluster->connection_graph)
if (IdString(node.cell_type) == cell->type)
if (node.idx != 0 && cell->name != ci->name ||
node.idx == 0 && cell->name == ci->name ){
if (node.idx != 0 && cell->name != ci->name || node.idx == 0 && cell->name == ci->name) {
idx_to_cells[node.idx].insert(cell);
}
@ -714,7 +722,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
std::queue<std::pair<uint32_t, uint32_t>> workqueue;
for (const auto &arc : idx_to_cells)
for (const auto &connection : cluster->connection_graph[arc.first].connections)
workqueue.push(std::pair<uint32_t, uint32_t>(arc.first, connection.target_idx));
workqueue.emplace(arc.first, connection.target_idx);
binary_constraint_check(cluster, workqueue, idx_to_cells, ctx);
for (const auto &arc : idx_to_cells) {
@ -775,7 +783,8 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
removequeue.push(std::pair<uint32_t, CellInfo *>(idx, *arc.second.begin()));
}
while (!removequeue.empty()) {
auto t = removequeue.front(); removequeue.pop();
auto t = removequeue.front();
removequeue.pop();
uint32_t idx = t.first;
CellInfo *cell = t.second;
idx_to_cells[idx].erase(cell);
@ -832,7 +841,7 @@ void Arch::prepare_macro_cluster( const ClusterPOD *cluster, uint32_t index)
cluster_info.root = ci;
cluster_info.index = index;
cluster_info.cluster_nodes.resize(idx_to_cells.size());
ci->cluster.set(ctx, ci->name.str(ctx));
ci->cluster = ci->name;
for (auto &arc : idx_to_cells) {
CellInfo *sub_cell = arc.second.pop();
if (ctx->verbose)
@ -1047,12 +1056,11 @@ void Arch::pack_cluster()
} else if (chip_info->clusters[i].physical_placements.size() > 0) {
const auto &cluster = chip_info->clusters[i];
if (ctx->verbose) {
log_info("%s\n", IdString(cluster.name).c_str(ctx));\
log_info("%s\n", IdString(cluster.name).c_str(ctx));
}
prepare_macro_cluster(&cluster, i);
}
else {
} else {
// No physical placement definitions found for given macro.
// Use default place and route algorithm as routes connectiong
// cells will use global routing

8
fpga_interchange/chipdb.h
View File

@ -428,9 +428,7 @@ NPNR_PACKED_STRUCT(struct ClusterRequiredCellPOD{
uint32_t count;
});
NPNR_PACKED_STRUCT(struct ClusterUsedPortPOD{
uint32_t name;
});
NPNR_PACKED_STRUCT(struct ClusterUsedPortPOD { uint32_t name; });
NPNR_PACKED_STRUCT(struct ClusterEdgePOD {
uint32_t dir;
@ -451,9 +449,7 @@ NPNR_PACKED_STRUCT(struct ClusterConnectionGraphPOD{
RelSlice<ClusterUsedPortPOD> used_ports;
});
NPNR_PACKED_STRUCT(struct ClusterPhysicalPlacementEntryPOD{
RelSlice<uint32_t> bels;
});
NPNR_PACKED_STRUCT(struct ClusterPhysicalPlacementEntryPOD { RelSlice<uint32_t> bels; });
NPNR_PACKED_STRUCT(struct ClusterPhysicalPlacementsPOD {
uint32_t site_type;

2
fpga_interchange/macros.cc
View File

@ -79,7 +79,6 @@ void Arch::expand_macros()
// Get the ultimate root of this macro expansion
IdString parent = (cell->macro_parent == IdString()) ? cell->name : cell->macro_parent;
log_info("%s %s\n", cell->name.c_str(ctx), parent.c_str(ctx));
// Create child instances
for (const auto &inst : macro->cell_insts) {
CellInfo *inst_cell =
@ -88,7 +87,6 @@ void Arch::expand_macros()
inst_cell->params[IdString(param.key)] = IdString(param.value).str(ctx);
}
inst_cell->macro_parent = parent;
log_info(" %s %s\n", inst_cell->name.c_str(ctx), inst_cell->type.c_str(ctx));
next_cells.push_back(inst_cell);
}
// Create and connect nets