ecp5: Begin planning data structures
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
parent
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639
ecp5/arch.h
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639
ecp5/arch.h
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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/**** Everything in this section must be kept in sync with chipdb.py ****/
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template <typename T> struct RelPtr
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{
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int32_t offset;
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// void set(const T *ptr) {
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// offset = reinterpret_cast<const char*>(ptr) -
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// reinterpret_cast<const char*>(this);
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// }
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const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
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const T &operator[](size_t index) const { return get()[index]; }
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const T &operator*() const { return *(get()); }
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const T *operator->() const { return get(); }
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};
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NPNR_PACKED_STRUCT(struct BelWirePOD {
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Location rel_wire_loc;
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int32_t wire_index;
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PortPin port;
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});
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NPNR_PACKED_STRUCT(struct BelInfoPOD {
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RelPtr<char> name;
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BelType type;
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct BelPortPOD {
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Location rel_bel_loc;
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int32_t bel_index;
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PortPin port;
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});
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NPNR_PACKED_STRUCT(struct PipInfoPOD {
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Location rel_src_loc, rel_dst_loc;
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int32_t src_idx, dst_idx;
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int32_t delay;
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Location rel_tile_loc;
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int16_t tile_type;
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int8_t pip_type;
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int8_t padding_0;
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});
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NPNR_PACKED_STRUCT(struct PipLocatorPOD {
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Location rel_loc;
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int32_t index;
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});
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NPNR_PACKED_STRUCT(struct WireInfoPOD {
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RelPtr<char> name;
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int32_t num_uphill, num_downhill;
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RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
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int32_t num_bels_downhill;
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BelPortPOD bel_uphill;
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RelPtr<BelPortPOD> bels_downhill;
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});
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NPNR_PACKED_STRUCT(struct LocationTypePOD {
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int32_t num_bels, num_wires, num_pips;
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RelPtr<BelInfoPOD> bel_data;
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RelPtr<WireInfoPOD> wire_data;
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RelPtr<PipInfoPOD> pip_data;
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});
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NPNR_PACKED_STRUCT(struct ChipInfoPOD {
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int32_t width, height;
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int32_t num_location_types;
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RelPtr<LocationTypePOD> locations;
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RelPtr<int32_t> location_type;
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});
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#if defined(_MSC_VER)
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extern const char *chipdb_blob_384;
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extern const char *chipdb_blob_1k;
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extern const char *chipdb_blob_5k;
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extern const char *chipdb_blob_8k;
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#else
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extern const char chipdb_blob_384[];
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extern const char chipdb_blob_1k[];
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extern const char chipdb_blob_5k[];
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extern const char chipdb_blob_8k[];
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#endif
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/************************ End of chipdb section. ************************/
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struct BelIterator
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{
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int cursor;
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BelIterator operator++()
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{
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cursor++;
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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cursor++;
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return prior;
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}
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
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BelId operator*() const
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{
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BelId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPinIterator
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{
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const BelPortPOD *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const
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{
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BelPin ret;
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ret.bel.index = ptr->bel_index;
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ret.pin = ptr->port;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const
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{
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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const int *cursor = nullptr;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = *cursor;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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struct ArchArgs
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{
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enum
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{
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NONE,
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LP384,
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LP1K,
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LP8K,
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HX1K,
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HX8K,
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UP5K
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} type = NONE;
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std::string package;
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};
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struct Arch : BaseCtx
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{
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const ChipInfoPOD *chip_info;
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const PackageInfoPOD *package_info;
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mutable std::unordered_map<IdString, int> bel_by_name;
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mutable std::unordered_map<IdString, int> wire_by_name;
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mutable std::unordered_map<IdString, int> pip_by_name;
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std::vector<IdString> bel_to_cell;
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std::vector<IdString> wire_to_net;
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std::vector<IdString> pip_to_net;
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std::vector<IdString> switches_locked;
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName();
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IdString archId() const { return id("ice40"); }
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IdString archArgsToId(ArchArgs args) const;
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IdString belTypeToId(BelType type) const;
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BelType belTypeFromId(IdString id) const;
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IdString portPinToId(PortPin type) const;
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PortPin portPinFromId(IdString id) const;
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// -------------------------------------------------
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BelId getBelByName(IdString name) const;
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IdString getBelName(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return id(chip_info->bel_data[bel.index].name.get());
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}
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uint32_t getBelChecksum(BelId bel) const { return bel.index; }
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void bindBel(BelId bel, IdString cell, PlaceStrength strength)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel.index] == IdString());
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bel_to_cell[bel.index] = cell;
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cells[cell]->bel = bel;
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cells[cell]->belStrength = strength;
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}
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void unbindBel(BelId bel)
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{
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NPNR_ASSERT(bel != BelId());
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NPNR_ASSERT(bel_to_cell[bel.index] != IdString());
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cells[bel_to_cell[bel.index]]->bel = BelId();
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cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE;
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bel_to_cell[bel.index] = IdString();
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}
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bool checkBelAvail(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index] == IdString();
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}
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IdString getBoundBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index];
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}
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IdString getConflictingBelCell(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[bel.index];
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}
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor = 0;
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range.e.cursor = chip_info->num_bels;
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return range;
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}
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BelRange getBelsByType(BelType type) const
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{
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BelRange range;
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// FIXME
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#if 0
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if (type == "TYPE_A") {
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range.b.cursor = bels_type_a_begin;
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range.e.cursor = bels_type_a_end;
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}
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...
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#endif
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return range;
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}
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BelRange getBelsAtSameTile(BelId bel) const;
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BelType getBelType(BelId bel) const
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{
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NPNR_ASSERT(bel != BelId());
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return chip_info->bel_data[bel.index].type;
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}
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WireId getWireBelPin(BelId bel, PortPin pin) const;
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BelPin getBelPinUphill(WireId wire) const
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{
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BelPin ret;
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NPNR_ASSERT(wire != WireId());
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if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
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}
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return ret;
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}
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BelPinRange getBelPinsDownhill(WireId wire) const
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{
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BelPinRange range;
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NPNR_ASSERT(wire != WireId());
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range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
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range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
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return range;
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}
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// -------------------------------------------------
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return id(chip_info->wire_data[wire.index].name.get());
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}
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uint32_t getWireChecksum(WireId wire) const { return wire.index; }
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void bindWire(WireId wire, IdString net, PlaceStrength strength)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] == IdString());
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wire_to_net[wire.index] = net;
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nets[net]->wires[wire].pip = PipId();
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nets[net]->wires[wire].strength = strength;
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}
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void unbindWire(WireId wire)
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire.index] != IdString());
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auto &net_wires = nets[wire_to_net[wire.index]]->wires;
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip_to_net[pip.index] = IdString();
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switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
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}
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net_wires.erase(it);
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wire_to_net[wire.index] = IdString();
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}
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bool checkWireAvail(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index] == IdString();
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}
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IdString getBoundWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index];
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}
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IdString getConflictingWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net[wire.index];
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}
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WireRange getWires() const
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{
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WireRange range;
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range.b.cursor = 0;
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range.e.cursor = chip_info->num_wires;
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return range;
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}
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// -------------------------------------------------
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PipId getPipByName(IdString name) const;
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IdString getPipName(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const { return pip.index; }
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void bindPip(PipId pip, IdString net, PlaceStrength strength)
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip.index] == IdString());
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NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString());
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pip_to_net[pip.index] = net;
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switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
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WireId dst;
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dst.index = chip_info->pip_data[pip.index].dst;
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NPNR_ASSERT(wire_to_net[dst.index] == IdString());
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wire_to_net[dst.index] = net;
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nets[net]->wires[dst].pip = pip;
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nets[net]->wires[dst].strength = strength;
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}
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void unbindPip(PipId pip)
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip.index] != IdString());
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NPNR_ASSERT(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString());
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WireId dst;
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dst.index = chip_info->pip_data[pip.index].dst;
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NPNR_ASSERT(wire_to_net[dst.index] != IdString());
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wire_to_net[dst.index] = IdString();
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nets[pip_to_net[pip.index]]->wires.erase(dst);
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pip_to_net[pip.index] = IdString();
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switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
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}
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bool checkPipAvail(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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return switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString();
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}
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IdString getBoundPipNet(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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return pip_to_net[pip.index];
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}
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IdString getConflictingPipNet(PipId pip) const
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{
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NPNR_ASSERT(pip != PipId());
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return switches_locked[chip_info->pip_data[pip.index].switch_index];
|
||||
}
|
||||
|
||||
AllPipRange getPips() const
|
||||
{
|
||||
AllPipRange range;
|
||||
range.b.cursor = 0;
|
||||
range.e.cursor = chip_info->num_pips;
|
||||
return range;
|
||||
}
|
||||
|
||||
WireId getPipSrcWire(PipId pip) const
|
||||
{
|
||||
WireId wire;
|
||||
NPNR_ASSERT(pip != PipId());
|
||||
wire.index = chip_info->pip_data[pip.index].src;
|
||||
return wire;
|
||||
}
|
||||
|
||||
WireId getPipDstWire(PipId pip) const
|
||||
{
|
||||
WireId wire;
|
||||
NPNR_ASSERT(pip != PipId());
|
||||
wire.index = chip_info->pip_data[pip.index].dst;
|
||||
return wire;
|
||||
}
|
||||
|
||||
DelayInfo getPipDelay(PipId pip) const
|
||||
{
|
||||
DelayInfo delay;
|
||||
NPNR_ASSERT(pip != PipId());
|
||||
delay.delay = chip_info->pip_data[pip.index].delay;
|
||||
return delay;
|
||||
}
|
||||
|
||||
PipRange getPipsDownhill(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
NPNR_ASSERT(wire != WireId());
|
||||
range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
|
||||
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
|
||||
return range;
|
||||
}
|
||||
|
||||
PipRange getPipsUphill(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
NPNR_ASSERT(wire != WireId());
|
||||
range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
|
||||
range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
|
||||
return range;
|
||||
}
|
||||
|
||||
PipRange getWireAliases(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
NPNR_ASSERT(wire != WireId());
|
||||
range.b.cursor = nullptr;
|
||||
range.e.cursor = nullptr;
|
||||
return range;
|
||||
}
|
||||
|
||||
BelId getPackagePinBel(const std::string &pin) const;
|
||||
std::string getBelPackagePin(BelId bel) const;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
void estimatePosition(BelId bel, int &x, int &y, bool &gb) const;
|
||||
delay_t estimateDelay(WireId src, WireId dst) const;
|
||||
delay_t getDelayEpsilon() const { return 20; }
|
||||
delay_t getRipupDelayPenalty() const { return 200; }
|
||||
float getDelayNS(delay_t v) const { return v * 0.001; }
|
||||
uint32_t getDelayChecksum(delay_t v) const { return v; }
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
std::vector<GraphicElement> getFrameGraphics() const;
|
||||
std::vector<GraphicElement> getBelGraphics(BelId bel) const;
|
||||
std::vector<GraphicElement> getWireGraphics(WireId wire) const;
|
||||
std::vector<GraphicElement> getPipGraphics(PipId pip) const;
|
||||
|
||||
bool allGraphicsReload = false;
|
||||
bool frameGraphicsReload = false;
|
||||
std::unordered_set<BelId> belGraphicsReload;
|
||||
std::unordered_set<WireId> wireGraphicsReload;
|
||||
std::unordered_set<PipId> pipGraphicsReload;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
// Get the delay through a cell from one port to another, returning false
|
||||
// if no path exists
|
||||
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
|
||||
// Get the associated clock to a port, or empty if the port is combinational
|
||||
IdString getPortClock(const CellInfo *cell, IdString port) const;
|
||||
// Return true if a port is a clock
|
||||
bool isClockPort(const CellInfo *cell, IdString port) const;
|
||||
// Return true if a port is a net
|
||||
bool isGlobalNet(const NetInfo *net) const;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc)
|
||||
|
||||
// Whether or not a given cell can be placed at a given Bel
|
||||
// This is not intended for Bel type checks, but finer-grained constraints
|
||||
// such as conflicting set/reset signals, etc
|
||||
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
||||
|
||||
// Return true whether all Bels at a given location are valid
|
||||
bool isBelLocationValid(BelId bel) const;
|
||||
|
||||
// Helper function for above
|
||||
bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
|
||||
|
||||
IdString id_glb_buf_out;
|
||||
IdString id_icestorm_lc, id_sb_io, id_sb_gb;
|
||||
IdString id_cen, id_clk, id_sr;
|
||||
IdString id_i0, id_i1, id_i2, id_i3;
|
||||
IdString id_dff_en, id_neg_clk;
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
126
ecp5/archdefs.h
Normal file
126
ecp5/archdefs.h
Normal file
@ -0,0 +1,126 @@
|
||||
/*
|
||||
* nextpnr -- Next Generation Place and Route
|
||||
*
|
||||
* Copyright (C) 2018 David Shah <david@symbioticeda.com>
|
||||
* Copyright (C) 2018 Clifford Wolf <clifford@symbioticeda.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef NEXTPNR_H
|
||||
#error Include "archdefs.h" via "nextpnr.h" only.
|
||||
#endif
|
||||
|
||||
NEXTPNR_NAMESPACE_BEGIN
|
||||
|
||||
typedef int delay_t;
|
||||
|
||||
struct DelayInfo
|
||||
{
|
||||
delay_t delay = 0;
|
||||
|
||||
delay_t raiseDelay() const { return delay; }
|
||||
delay_t fallDelay() const { return delay; }
|
||||
delay_t avgDelay() const { return delay; }
|
||||
|
||||
DelayInfo operator+(const DelayInfo &other) const
|
||||
{
|
||||
DelayInfo ret;
|
||||
ret.delay = this->delay + other.delay;
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
||||
enum BelType : int32_t
|
||||
{
|
||||
TYPE_NONE,
|
||||
TYPE_TRELLIS_SLICE,
|
||||
TYPE_TRELLIS_IO
|
||||
};
|
||||
|
||||
enum PortPin : int32_t
|
||||
{
|
||||
PIN_NONE,
|
||||
#define X(t) PIN_##t,
|
||||
#include "portpins.inc"
|
||||
#undef X
|
||||
PIN_MAXIDX
|
||||
};
|
||||
|
||||
NPNR_PACKED_STRUCT(
|
||||
struct Location {
|
||||
int16_t x = -1, y = -1;
|
||||
bool operator==(const Location &other) const { return x == other.x && y == other.y; }
|
||||
bool operator!=(const Location &other) const { return x != other.x || y == other.y; }
|
||||
}
|
||||
);
|
||||
|
||||
struct BelId
|
||||
{
|
||||
Location location;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const BelId &other) const { return index == other.index && location == other.location; }
|
||||
bool operator!=(const BelId &other) const { return index != other.index || location != other.location; }
|
||||
};
|
||||
|
||||
struct WireId
|
||||
{
|
||||
Location location;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const WireId &other) const { return index == other.index && location == other.location; }
|
||||
bool operator!=(const WireId &other) const { return index != other.index || location != other.location; }
|
||||
};
|
||||
|
||||
struct PipId
|
||||
{
|
||||
Location location;
|
||||
int32_t index = -1;
|
||||
|
||||
bool operator==(const WireId &other) const { return index == other.index && location == other.location; }
|
||||
bool operator!=(const WireId &other) const { return index != other.index || location != other.location; }
|
||||
};
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
namespace std {
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept { return hash<int>()(bel.index); }
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
|
||||
{
|
||||
return hash<int>()(wire.index);
|
||||
}
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
|
||||
{
|
||||
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept { return hash<int>()(pip.index); }
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelType> : hash<int>
|
||||
{
|
||||
};
|
||||
|
||||
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PortPin> : hash<int>
|
||||
{
|
||||
};
|
||||
} // namespace std
|
||||
28
ecp5/portpins.inc
Normal file
28
ecp5/portpins.inc
Normal file
@ -0,0 +1,28 @@
|
||||
X(A0)
|
||||
X(B0)
|
||||
X(C0)
|
||||
X(D0)
|
||||
X(A1)
|
||||
X(B1)
|
||||
X(C1)
|
||||
X(D1)
|
||||
X(M0)
|
||||
X(M1)
|
||||
X(FCI)
|
||||
X(FXA)
|
||||
X(FXB)
|
||||
X(CLK)
|
||||
X(LSR)
|
||||
X(CE)
|
||||
X(F0)
|
||||
X(Q0)
|
||||
X(F1)
|
||||
X(Q1)
|
||||
X(FCO)
|
||||
X(OFX0)
|
||||
X(OFX1)
|
||||
|
||||
X(I)
|
||||
X(O)
|
||||
X(T)
|
||||
X(B)
|
||||
Loading…
Reference in New Issue
Block a user