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awooter: partitioner improvements

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This commit is contained in:
Lofty 2022-11-28 21:15:04 +00:00
parent 181d76772a
commit eaf55a0b2e
2 changed files with 51 additions and 19 deletions
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34
common/route/awooter/rust/src/partition.rs
View File

@ -314,11 +314,17 @@ fn approximate_partition_results(
// but i can't be bothered (yes this is all copy-pasted from the actual partitioner)
let mut middle_horiz = (
partition_point.0,
split_line_over_x((arc.get_source_loc(), arc.get_sink_loc()), partition_point.0),
split_line_over_x(
(arc.get_source_loc(), arc.get_sink_loc()),
partition_point.0,
),
);
let mut middle_vert = (
split_line_over_y((arc.get_source_loc(), arc.get_sink_loc()), partition_point.1),
split_line_over_y(
(arc.get_source_loc(), arc.get_sink_loc()),
partition_point.1,
),
partition_point.1,
);
@ -928,7 +934,11 @@ pub fn find_partition_point_and_sanity_check(
|| arc.get_sink_loc().x <= x_start
|| arc.get_sink_loc().y <= y_start
{
println!("oob: {:?} -> {:?}", arc.get_source_loc(), arc.get_sink_loc());
println!(
"oob: {:?} -> {:?}",
arc.get_source_loc(),
arc.get_sink_loc()
);
out_of_bound_arcs_in_ne += 1;
}
}
@ -946,7 +956,11 @@ pub fn find_partition_point_and_sanity_check(
|| arc.get_sink_loc().x >= x_finish
|| arc.get_sink_loc().y <= y_start
{
println!("oob: {:?} -> {:?}", arc.get_source_loc(), arc.get_sink_loc());
println!(
"oob: {:?} -> {:?}",
arc.get_source_loc(),
arc.get_sink_loc()
);
out_of_bound_arcs_in_se += 1;
}
}
@ -964,7 +978,11 @@ pub fn find_partition_point_and_sanity_check(
|| arc.get_sink_loc().x >= x_finish
|| arc.get_sink_loc().y >= y_finish
{
println!("oob: {:?} -> {:?}", arc.get_source_loc(), arc.get_sink_loc());
println!(
"oob: {:?} -> {:?}",
arc.get_source_loc(),
arc.get_sink_loc()
);
out_of_bound_arcs_in_sw += 1;
}
}
@ -982,7 +1000,11 @@ pub fn find_partition_point_and_sanity_check(
|| arc.get_sink_loc().x <= x_start
|| arc.get_sink_loc().y >= y_finish
{
println!("oob: {:?} -> {:?}", arc.get_source_loc(), arc.get_sink_loc());
println!(
"oob: {:?} -> {:?}",
arc.get_source_loc(),
arc.get_sink_loc()
);
out_of_bound_arcs_in_nw += 1;
}
}

36
common/route/awooter/rust/src/route.rs
View File

@ -1,6 +1,7 @@
use std::{
collections::{BinaryHeap, HashMap, HashSet},
time::Instant, sync::RwLock,
sync::RwLock,
time::Instant,
};
use colored::Colorize;
@ -8,7 +9,7 @@ use indicatif::{MultiProgress, ProgressBar, ProgressStyle};
use itertools::Itertools;
use crate::{
npnr::{self, IdString, NetIndex, PipId, WireId, Loc},
npnr::{self, IdString, Loc, NetIndex, PipId, WireId},
partition,
};
@ -303,7 +304,10 @@ impl Router {
let mut next_arcs = Vec::new();
for arc in this.arcs {
for wire in self.nets.read().unwrap()[arc.net.into_inner() as usize].wires.keys() {
for wire in self.nets.read().unwrap()[arc.net.into_inner() as usize]
.wires
.keys()
{
if overused.contains(wire) {
next_arcs.push(arc);
}
@ -488,7 +492,9 @@ impl Router {
dirty_wires.push(source_wire);
dirty_wires.push(sink_wire);
let already_done = self.nets.read().unwrap()[arc.net().into_inner() as usize].done_sinks.contains(&arc.sink_wire);
let already_done = self.nets.read().unwrap()[arc.net().into_inner() as usize]
.done_sinks
.contains(&arc.sink_wire);
if already_done {
midpoint = Some(*self.wire_to_idx.get(&arc.sink_wire).unwrap());
@ -537,8 +543,14 @@ impl Router {
) {
break;
}*/
self.flat_wires[source_wire as usize].write().unwrap().visited_fwd = true;
self.flat_wires[sink_wire as usize].write().unwrap().visited_bwd = true;
self.flat_wires[source_wire as usize]
.write()
.unwrap()
.visited_fwd = true;
self.flat_wires[sink_wire as usize]
.write()
.unwrap()
.visited_bwd = true;
}
}
@ -561,9 +573,7 @@ impl Router {
};
assert!(pip != PipId::null());
let node_delay = ctx.pip_delay(pip)
+ ctx.wire_delay(wireid)
+ ctx.delay_epsilon();
let node_delay = ctx.pip_delay(pip) + ctx.wire_delay(wireid) + ctx.delay_epsilon();
calculated_delay += node_delay;
self.bind_pip_internal(arc.net(), wire, pip);
@ -579,14 +589,14 @@ impl Router {
// do note that the order is inverted from the fwd loop
wire = *self.wire_to_idx.get(&ctx.pip_dst_wire(pip)).unwrap();
let node_delay = ctx.pip_delay(pip)
+ ctx.wire_delay(wireid)
+ ctx.delay_epsilon();
let node_delay = ctx.pip_delay(pip) + ctx.wire_delay(wireid) + ctx.delay_epsilon();
calculated_delay += node_delay;
self.bind_pip_internal(arc.net(), wire, pip);
}
self.nets.write().unwrap()[arc.net().into_inner() as usize].done_sinks.insert(arc.sink_wire);
self.nets.write().unwrap()[arc.net().into_inner() as usize]
.done_sinks
.insert(arc.sink_wire);
self.reset_wires(&dirty_wires);