From eafc0e4e9e94edfb0626dc3817fa5d119e2a01f7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 6 Oct 2019 16:24:43 +0200
Subject: [PATCH] Added type to wire

---
 ecp5/arch.h            |  9 ++++++-
 ecp5/constids.inc      | 19 +++++++++++++
 ecp5/trellis_import.py | 60 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/ecp5/arch.h b/ecp5/arch.h
index 94bd5f3a..f6ba1a7b 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -84,6 +84,7 @@ NPNR_PACKED_STRUCT(struct PipLocatorPOD {
 
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
+    int32_t type;
     int32_t num_uphill, num_downhill;
     RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
 
@@ -639,7 +640,13 @@ struct Arch : BaseCtx
         return id(name.str());
     }
 
-    IdString getWireType(WireId wire) const { return IdString(); }
+    IdString getWireType(WireId wire) const
+    {
+        NPNR_ASSERT(wire != WireId());
+        IdString id;
+        id.index = locInfo(wire)->wire_data[wire.index].type;
+        return id;
+    }
 
     std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const
     {
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 5e8fc7da..f7d722c1 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1294,3 +1294,22 @@ X(P)
 X(ECLKBRIDGECS)
 X(SEL)
 X(ECSOUT)
+
+X(WIRE_TYPE_NONE)
+X(WIRE_TYPE_SLICE)
+X(WIRE_TYPE_H00R)
+X(WIRE_TYPE_H00L)
+X(WIRE_TYPE_H01E)
+X(WIRE_TYPE_H01W)
+X(WIRE_TYPE_H02E)
+X(WIRE_TYPE_H02W)
+X(WIRE_TYPE_H06E)
+X(WIRE_TYPE_H06W)
+X(WIRE_TYPE_V00T)
+X(WIRE_TYPE_V00B)
+X(WIRE_TYPE_V01N)
+X(WIRE_TYPE_V01S)
+X(WIRE_TYPE_V02N)
+X(WIRE_TYPE_V02S)
+X(WIRE_TYPE_V06N)
+X(WIRE_TYPE_V06S)
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 610bd331..188c6909 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -16,6 +16,65 @@ parser.add_argument("device", type=str, help="target device")
 parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
 args = parser.parse_args()
 
+def wire_type(name):
+    longname = name
+    name = name.split('/')
+
+    if name[0].startswith("X") and name[1].startswith("Y"):
+        name = name[2:]
+
+    if name[0].endswith("_SLICE"):
+        return "WIRE_TYPE_SLICE"
+
+    if name[0].startswith("H00R"):
+        return "WIRE_TYPE_H00R"
+
+    if name[0].startswith("H00L"):
+        return "WIRE_TYPE_H00L"
+
+    if name[0].startswith("H01E"):
+        return "WIRE_TYPE_H01E"
+
+    if name[0].startswith("H01W"):
+        return "WIRE_TYPE_H01W"
+
+    if name[0].startswith("H02E"):
+        return "WIRE_TYPE_H02E"
+
+    if name[0].startswith("H02W"):
+        return "WIRE_TYPE_H02W"
+
+    if name[0].startswith("H06E"):
+        return "WIRE_TYPE_H06E"
+
+    if name[0].startswith("H06W"):
+        return "WIRE_TYPE_H06W"
+
+    if name[0].startswith("V00T"):
+        return "WIRE_TYPE_V00T"
+
+    if name[0].startswith("V00B"):
+        return "WIRE_TYPE_V00B"
+
+    if name[0].startswith("V01N"):
+        return "WIRE_TYPE_V01N"
+
+    if name[0].startswith("V01S"):
+        return "WIRE_TYPE_V01S"
+
+    if name[0].startswith("V02N"):
+        return "WIRE_TYPE_V02N"
+
+    if name[0].startswith("V02S"):
+        return "WIRE_TYPE_V02S"
+
+    if name[0].startswith("V06N"):
+        return "WIRE_TYPE_V06N"
+
+    if name[0].startswith("V06S"):
+        return "WIRE_TYPE_V06S"
+
+    return "WIRE_TYPE_NONE"
 
 def is_global(loc):
     return loc.x == -2 and loc.y == -2
@@ -298,6 +357,7 @@ def write_database(dev_name, chip, ddrg, endianness):
             for wire_idx in range(len(loctype.wires)):
                 wire = loctype.wires[wire_idx]
                 bba.s(ddrg.to_str(wire.name), "name")
+                bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
                 bba.u32(len(wire.arcsUphill), "num_uphill")
                 bba.u32(len(wire.arcsDownhill), "num_downhill")
                 bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")