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more new wires added

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This commit is contained in:
Miodrag Milanovic 2019-12-14 09:18:24 +01:00
parent 19eb16045f
commit ebbfb6375d
5 changed files with 214 additions and 2 deletions
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11
ecp5/arch.cc
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@ -723,7 +723,16 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const
el.y1 = y + slice_y1;
el.y2 = y + slice_y2;
ret.push_back(el);
} else if (bel_type == id_DCUA || bel_type == id_EXTREFB || bel_type == id_PCSCLKDIV || bel_type == id_DTR ||
} else if (bel_type == id_DCUA) {
GraphicElement el;
el.type = GraphicElement::TYPE_BOX;
el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE;
el.x1 = x + slice_x1;
el.x2 = x + 0.97;
el.y1 = y + slice_y2;
el.y2 = y + 0.25;
ret.push_back(el);
} else if (bel_type == id_EXTREFB || bel_type == id_PCSCLKDIV || bel_type == id_DTR ||
bel_type == id_USRMCLK) {
GraphicElement el;
el.type = GraphicElement::TYPE_BOX;

7
ecp5/constids.inc
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@ -1308,6 +1308,13 @@ X(WIRE_TYPE_DDRDLL)
X(WIRE_TYPE_CCLK)
X(WIRE_TYPE_EXTREF)
X(WIRE_TYPE_DCU)
X(WIRE_TYPE_PLL)
X(WIRE_TYPE_SED)
X(WIRE_TYPE_OSC)
X(WIRE_TYPE_JTAG)
X(WIRE_TYPE_GSR)
X(WIRE_TYPE_DTR)
X(WIRE_TYPE_PCSCLKDIV)
X(WIRE_TYPE_H00)
X(WIRE_TYPE_H01)

95
ecp5/gfx.cc
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@ -211,6 +211,101 @@ void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdS
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_PLL) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_CLKI_PLL + 1);
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_GSR) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_JCLK_GSR + 1);
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_JTAG) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_JJCE1_JTAG + 1) + 1 * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_OSC) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_SEDSTDBY_OSC + 1) + 2 * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_SED) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_SEDSTDBY_SED + 1) + 3 * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_DTR) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_JSTARTPULSE_DTR + 1);
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_EXTREF) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_REFCLKP_EXTREF + 1) + 1 * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_DCU) {
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (tilewire - TILE_WIRE_CH0_RX_REFCLK_DCU + 1) + 0 * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_PCSCLKDIV) {
int num = (tilewire - TILE_WIRE_CLKI_PCSCLKDIV1) % 7;
int group = 1-(tilewire - TILE_WIRE_CLKI_PCSCLKDIV1) / 7;
GraphicElement el;
el.type = GraphicElement::TYPE_LINE;
el.style = style;
el.x1 = x + slice_x1 - 0.005f;
el.x2 = x + slice_x1;
el.y1 = y + slice_y2 - 0.0017f * (num + 1) + group * slice_pitch;
el.y2 = el.y1;
g.push_back(el);
}
if (wire_type == id_WIRE_TYPE_V01) {
if (tilewire >= TILE_WIRE_V01N0001 && tilewire <= TILE_WIRE_V01S0100) {
GraphicElement el;

79
ecp5/gfx.h
View File

@ -2057,8 +2057,85 @@ enum GfxTileWireId
TILE_WIRE_G_CLKO_LDCC12,
TILE_WIRE_G_CLKI_LDCC13,
TILE_WIRE_G_JCE_LDCC13,
TILE_WIRE_G_CLKO_LDCC13
TILE_WIRE_G_CLKO_LDCC13,
TILE_WIRE_CLKI_PLL,
TILE_WIRE_JRST_PLL,
TILE_WIRE_JLOCK_PLL,
TILE_WIRE_CLKFB_PLL,
TILE_WIRE_CLKINTFB_PLL,
TILE_WIRE_JREFCLK_PLL,
TILE_WIRE_JSTDBY_PLL,
TILE_WIRE_JPHASEDIR_PLL,
TILE_WIRE_JPHASELOADREG_PLL,
TILE_WIRE_JPHASESEL0_PLL,
TILE_WIRE_JPHASESEL1_PLL,
TILE_WIRE_JPHASESTEP_PLL,
TILE_WIRE_JPLLWAKESYNC_PLL,
TILE_WIRE_JENCLKOP_PLL,
TILE_WIRE_JENCLKOS2_PLL,
TILE_WIRE_JENCLKOS3_PLL,
TILE_WIRE_JENCLKOS_PLL,
TILE_WIRE_JINTLOCK_PLL,
TILE_WIRE_JCLKOP_PLL,
TILE_WIRE_JCLKOS_PLL,
TILE_WIRE_JCLKOS2_PLL,
TILE_WIRE_JCLKOS3_PLL,
TILE_WIRE_SEDSTDBY_SED,
TILE_WIRE_JSEDENABLE_SED,
TILE_WIRE_JSEDSTART_SED,
TILE_WIRE_JSEDFRCERR_SED,
TILE_WIRE_JSEDDONE_SED,
TILE_WIRE_JSEDINPROG_SED,
TILE_WIRE_JSEDERR_SED,
TILE_WIRE_SEDSTDBY_OSC,
TILE_WIRE_JJCE1_JTAG,
TILE_WIRE_JJCE2_JTAG,
TILE_WIRE_JTCK_JTAG,
TILE_WIRE_JTMS_JTAG,
TILE_WIRE_JTDI_JTAG,
TILE_WIRE_JJTDO2_JTAG,
TILE_WIRE_JJTDO1_JTAG,
TILE_WIRE_JTDO_JTAG,
TILE_WIRE_JJTDI_JTAG,
TILE_WIRE_JJTCK_JTAG,
TILE_WIRE_JJRTI2_JTAG,
TILE_WIRE_JJRTI1_JTAG,
TILE_WIRE_JJSHIFT_JTAG,
TILE_WIRE_JJUPDATE_JTAG,
TILE_WIRE_JJRSTN_JTAG,
TILE_WIRE_JCLK_GSR,
TILE_WIRE_JGSR_GSR,
TILE_WIRE_JSTARTPULSE_DTR,
TILE_WIRE_JDTROUT0_DTR,
TILE_WIRE_JDTROUT1_DTR,
TILE_WIRE_JDTROUT2_DTR,
TILE_WIRE_JDTROUT3_DTR,
TILE_WIRE_JDTROUT4_DTR,
TILE_WIRE_JDTROUT5_DTR,
TILE_WIRE_JDTROUT6_DTR,
TILE_WIRE_JDTROUT7_DTR,
TILE_WIRE_CLKI_PCSCLKDIV1,
TILE_WIRE_JRST_PCSCLKDIV1,
TILE_WIRE_CDIVX_PCSCLKDIV1,
TILE_WIRE_JSEL0_PCSCLKDIV1,
TILE_WIRE_JSEL1_PCSCLKDIV1,
TILE_WIRE_JSEL2_PCSCLKDIV1,
TILE_WIRE_CDIV1_PCSCLKDIV1,
TILE_WIRE_CLKI_PCSCLKDIV0,
TILE_WIRE_JRST_PCSCLKDIV0,
TILE_WIRE_CDIVX_PCSCLKDIV0,
TILE_WIRE_JSEL0_PCSCLKDIV0,
TILE_WIRE_JSEL1_PCSCLKDIV0,
TILE_WIRE_JSEL2_PCSCLKDIV0,
TILE_WIRE_CDIV1_PCSCLKDIV0
};
void gfxTileWire(std::vector<GraphicElement> &g, int x, int y, int w, int h, IdString wire_type, GfxTileWireId tilewire,

24
ecp5/trellis_import.py
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@ -83,6 +83,30 @@ def wire_type(name):
if name[0].endswith("_ALU54"):
return "WIRE_TYPE_ALU54"
if name[0].endswith("_PLL"):
return "WIRE_TYPE_PLL"
if name[0].endswith("_SED"):
return "WIRE_TYPE_SED"
if name[0].endswith("_OSC"):
return "WIRE_TYPE_OSC"
if name[0].endswith("_JTAG"):
return "WIRE_TYPE_JTAG"
if name[0].endswith("_GSR"):
return "WIRE_TYPE_GSR"
if name[0].endswith("_DTR"):
return "WIRE_TYPE_DTR"
if name[0].endswith("_PCSCLKDIV0"):
return "WIRE_TYPE_PCSCLKDIV"
if name[0].endswith("_PCSCLKDIV1"):
return "WIRE_TYPE_PCSCLKDIV"
if name[0].startswith("H00"):
return "WIRE_TYPE_H00"