caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ice40: Removing deprecated API in cells.cc

Browse Source 
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-19 10:50:23 +02:00
parent 79d1075345
commit ec2792764a
1 changed files with 46 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

91
ice40/cells.cc
View File

@ -24,10 +24,11 @@
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
static void add_port(const Context *ctx, CellInfo *cell, IdString name, void add_port(const Context *ctx, CellInfo *cell, std::string name,
PortType dir) PortType dir)
{ {
cell->ports[name] = PortInfo{name, nullptr, dir}; IdString id = ctx->id(name);
cell->ports[id] = PortInfo{id, nullptr, dir};
} }
CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name) CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name)
@ -41,13 +42,13 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name)
new_cell->name = name; new_cell->name = name;
} }
new_cell->type = type; new_cell->type = type;
if (type == "ICESTORM_LC") { if (type == ctx->id("ICESTORM_LC")) {
new_cell->params["LUT_INIT"] = "0"; new_cell->params[ctx->id("LUT_INIT")] = "0";
new_cell->params["NEG_CLK"] = "0"; new_cell->params[ctx->id("NEG_CLK")] = "0";
new_cell->params["CARRY_ENABLE"] = "0"; new_cell->params[ctx->id("CARRY_ENABLE")] = "0";
new_cell->params["DFF_ENABLE"] = "0"; new_cell->params[ctx->id("DFF_ENABLE")] = "0";
new_cell->params["SET_NORESET"] = "0"; new_cell->params[ctx->id("SET_NORESET")] = "0";
new_cell->params["ASYNC_SR"] = "0"; new_cell->params[ctx->id("ASYNC_SR")] = "0";
add_port(ctx, new_cell, "I0", PORT_IN); add_port(ctx, new_cell, "I0", PORT_IN);
add_port(ctx, new_cell, "I1", PORT_IN); add_port(ctx, new_cell, "I1", PORT_IN);
@ -62,11 +63,11 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name)
add_port(ctx, new_cell, "LO", PORT_OUT); add_port(ctx, new_cell, "LO", PORT_OUT);
add_port(ctx, new_cell, "O", PORT_OUT); add_port(ctx, new_cell, "O", PORT_OUT);
add_port(ctx, new_cell, "OUT", PORT_OUT); add_port(ctx, new_cell, "OUT", PORT_OUT);
} else if (type == "SB_IO") { } else if (type == ctx->id("SB_IO")) {
new_cell->params["PIN_TYPE"] = "0"; new_cell->params[ctx->id("PIN_TYPE")] = "0";
new_cell->params["PULLUP"] = "0"; new_cell->params[ctx->id("PULLUP")] = "0";
new_cell->params["NEG_TRIGGER"] = "0"; new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
new_cell->params["IOSTANDARD"] = "SB_LVCMOS"; new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS";
add_port(ctx, new_cell, "PACKAGE_PIN", PORT_INOUT); add_port(ctx, new_cell, "PACKAGE_PIN", PORT_INOUT);
@ -81,11 +82,11 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name)
add_port(ctx, new_cell, "D_IN_0", PORT_OUT); add_port(ctx, new_cell, "D_IN_0", PORT_OUT);
add_port(ctx, new_cell, "D_IN_1", PORT_OUT); add_port(ctx, new_cell, "D_IN_1", PORT_OUT);
} else if (type == "ICESTORM_RAM") { } else if (type == ctx->id("ICESTORM_RAM")) {
new_cell->params["NEG_CLK_W"] = "0"; new_cell->params[ctx->id("NEG_CLK_W")] = "0";
new_cell->params["NEG_CLK_R"] = "0"; new_cell->params[ctx->id("NEG_CLK_R")] = "0";
new_cell->params["WRITE_MODE"] = "0"; new_cell->params[ctx->id("WRITE_MODE")] = "0";
new_cell->params["READ_MODE"] = "0"; new_cell->params[ctx->id("READ_MODE")] = "0";
add_port(ctx, new_cell, "RCLK", PORT_IN); add_port(ctx, new_cell, "RCLK", PORT_IN);
add_port(ctx, new_cell, "RCLKE", PORT_IN); add_port(ctx, new_cell, "RCLKE", PORT_IN);
@ -105,7 +106,7 @@ CellInfo *create_ice_cell(Context *ctx, IdString type, IdString name)
add_port(ctx, new_cell, "RADDR_" + std::to_string(i), PORT_IN); add_port(ctx, new_cell, "RADDR_" + std::to_string(i), PORT_IN);
add_port(ctx, new_cell, "WADDR_" + std::to_string(i), PORT_IN); add_port(ctx, new_cell, "WADDR_" + std::to_string(i), PORT_IN);
} }
} else if (type == "SB_GB") { } else if (type == ctx->id("SB_GB")) {
add_port(ctx, new_cell, "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN); add_port(ctx, new_cell, "USER_SIGNAL_TO_GLOBAL_BUFFER", PORT_IN);
add_port(ctx, new_cell, "GLOBAL_BUFFER_OUTPUT", PORT_OUT); add_port(ctx, new_cell, "GLOBAL_BUFFER_OUTPUT", PORT_OUT);
} else { } else {
@ -130,16 +131,16 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
bool pass_thru_lut) bool pass_thru_lut)
{ {
lc->params["DFF_ENABLE"] = "1"; lc->params[ctx->id("DFF_ENABLE")] = "1";
std::string config = dff->type.str().substr(6); std::string config = dff->type.str(ctx).substr(6);
auto citer = config.begin(); auto citer = config.begin();
replace_port(dff, "C", lc, "CLK"); replace_port(dff, "C", lc, "CLK");
if (citer != config.end() && *citer == 'N') { if (citer != config.end() && *citer == 'N') {
lc->params["NEG_CLK"] = "1"; lc->params[ctx->id("NEG_CLK")] = "1";
++citer; ++citer;
} else { } else {
lc->params["NEG_CLK"] = "0"; lc->params[ctx->id("NEG_CLK")] = "0";
} }
if (citer != config.end() && *citer == 'E') { if (citer != config.end() && *citer == 'E') {
@ -151,27 +152,27 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
if ((config.end() - citer) >= 2) { if ((config.end() - citer) >= 2) {
char c = *(citer++); char c = *(citer++);
assert(c == 'S'); assert(c == 'S');
lc->params["ASYNC_SR"] = "0"; lc->params[ctx->id("ASYNC_SR")] = "0";
} else { } else {
lc->params["ASYNC_SR"] = "1"; lc->params[ctx->id("ASYNC_SR")] = "1";
} }
if (*citer == 'S') { if (*citer == 'S') {
citer++; citer++;
replace_port(dff, "S", lc, "SR"); replace_port(dff, "S", lc, "SR");
lc->params["SET_NORESET"] = "1"; lc->params[ctx->id("SET_NORESET")] = "1";
} else { } else {
assert(*citer == 'R'); assert(*citer == 'R');
citer++; citer++;
replace_port(dff, "R", lc, "SR"); replace_port(dff, "R", lc, "SR");
lc->params["SET_NORESET"] = "0"; lc->params[ctx->id("SET_NORESET")] = "0";
} }
} }
assert(citer == config.end()); assert(citer == config.end());
if (pass_thru_lut) { if (pass_thru_lut) {
lc->params["LUT_INIT"] = "2"; lc->params[ctx->id("LUT_INIT")] = "2";
replace_port(dff, "D", lc, "I0"); replace_port(dff, "D", lc, "I0");
} }
@ -180,14 +181,14 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc,
void nxio_to_sb(const Context *ctx, CellInfo *nxio, CellInfo *sbio) void nxio_to_sb(const Context *ctx, CellInfo *nxio, CellInfo *sbio)
{ {
if (nxio->type == "$nextpnr_ibuf") { if (nxio->type == ctx->id("$nextpnr_ibuf")) {
sbio->params["PIN_TYPE"] = "1"; sbio->params[ctx->id("PIN_TYPE")] = "1";
auto pu_attr = nxio->attrs.find("PULLUP"); auto pu_attr = nxio->attrs.find("PULLUP");
if (pu_attr != nxio->attrs.end()) if (pu_attr != nxio->attrs.end())
sbio->params["PULLUP"] = pu_attr->second; sbio->params[ctx->id("PULLUP")] = pu_attr->second;
replace_port(nxio, "O", sbio, "D_IN_0"); replace_port(nxio, "O", sbio, "D_IN_0");
} else if (nxio->type == "$nextpnr_obuf") { } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
sbio->params["PIN_TYPE"] = "25"; sbio->params[ctx->id("PIN_TYPE")] = "25";
replace_port(nxio, "I", sbio, "D_OUT_0"); replace_port(nxio, "I", sbio, "D_OUT_0");
} else { } else {
assert(false); assert(false);
@ -199,11 +200,11 @@ bool is_clock_port(const Context *ctx, const PortRef &port)
if (port.cell == nullptr) if (port.cell == nullptr)
return false; return false;
if (is_ff(ctx, port.cell)) if (is_ff(ctx, port.cell))
return port.port == "C"; return port.port == ctx->id("C");
if (port.cell->type == "ICESTORM_LC") if (port.cell->type == ctx->id("ICESTORM_LC"))
return port.port == "CLK"; return port.port == ctx->id("CLK");
if (is_ram(ctx, port.cell) || port.cell->type == "ICESTORM_RAM") if (is_ram(ctx, port.cell) || port.cell->type == ctx->id("ICESTORM_RAM"))
return port.port == "RCLK" || port.port == "WCLK"; return port.port == ctx->id("RCLK") || port.port == ctx->id("WCLK");
return false; return false;
} }
@ -212,9 +213,9 @@ bool is_reset_port(const Context *ctx, const PortRef &port)
if (port.cell == nullptr) if (port.cell == nullptr)
return false; return false;
if (is_ff(ctx, port.cell)) if (is_ff(ctx, port.cell))
return port.port == "R" || port.port == "S"; return port.port == ctx->id("R") || port.port == ctx->id("S");
if (port.cell->type == "ICESTORM_LC") if (port.cell->type == ctx->id("ICESTORM_LC"))
return port.port == "SR"; return port.port == ctx->id("SR");
return false; return false;
} }
@ -223,9 +224,9 @@ bool is_enable_port(const Context *ctx, const PortRef &port)
if (port.cell == nullptr) if (port.cell == nullptr)
return false; return false;
if (is_ff(ctx, port.cell)) if (is_ff(ctx, port.cell))
return port.port == "E"; return port.port == ctx->id("E");
if (port.cell->type == "ICESTORM_LC") if (port.cell->type == ctx->id("ICESTORM_LC"))
return port.port == "CEN"; return port.port == ctx->id("CEN");
return false; return false;
} }