interchange: Add Nexus LUT test

Signed-off-by: gatecat <gatecat@ds0.me>

.github/workflows/interchange_ci.yml

@@ -67,7 +67,7 @@ jobs:
     needs: [Build-yosys, Build-nextpnr]
     strategy:
       matrix:
-        device: [xc7a35t, xc7a100t, xc7a200t, xc7z010]
+        device: [xc7a35t, xc7a100t, xc7a200t, xc7z010, LIFCL-17]
     steps:
 
     - uses: actions/checkout@v2

fpga_interchange/examples/chipdb.cmake

@@ -108,6 +108,8 @@ function(create_prjoxide_device_db)
             interchange-export
             ${device}
             ${prjoxide_device_db}
+        DEPENDS
+            ${PRJOXIDE_PREFIX}/bin/prjoxide
     )
 
     add_custom_target(prjoxide-${device}-device DEPENDS ${prjoxide_device_db})
@@ -208,6 +210,80 @@ function(create_patched_device_db)
     endif()
 endfunction()
 
+function(patch_device_with_prim_lib)
+    # ~~~
+    # patch_device_with_prim_lib(
+    #    device <common device>
+    #    yosys_script <yosys script>
+    #    input_device <input device target>
+    #    output_target <output device target>
+    # )
+    # ~~~
+    #
+    # Generates a patched device database starting from an input device
+    #
+    # If output_target is specified, the variable named as the output_target
+    # parameter value is set to the generated output_device_file target.
+    #
+    # Arguments:
+    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
+    #             share the same xc7a35t device prefix.
+    #   - yosys_script: yosys script to produce cell library
+    #   - input_device: target for the device that needs to be patched
+    #   - output_target: variable name that will hold the output device target for the parent scope
+    #
+    # Targets generated:
+    #   - prims-<device>-device
+
+    set(options)
+    set(oneValueArgs device yosys_script input_device output_target)
+    set(multiValueArgs)
+
+    cmake_parse_arguments(
+        patch_device_with_prim_lib
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(device ${patch_device_with_prim_lib_device})
+    set(yosys_script ${patch_device_with_prim_lib_yosys_script})
+    set(input_device ${patch_device_with_prim_lib_input_device})
+    set(output_target ${patch_device_with_prim_lib_output_target})
+
+    get_target_property(input_device_loc ${input_device} LOCATION)
+    set(output_device_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.device)
+    set(output_json_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.json)
+
+    add_custom_command(
+        OUTPUT ${output_json_file}
+        COMMAND
+            yosys -p '${yosys_script}\; write_json ${output_json_file}'
+    )
+
+    add_custom_command(
+        OUTPUT ${output_device_file}
+        COMMAND
+            ${PYTHON_EXECUTABLE} -mfpga_interchange.add_prim_lib
+                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+                ${input_device_loc}
+                ${output_json_file}
+                ${output_device_file}
+        DEPENDS
+            ${input_device}
+            ${input_device_loc}
+            ${output_json_file}
+    )
+
+    add_custom_target(prims-${device}-device DEPENDS ${output_device_file})
+    set_property(TARGET prims-${device}-device PROPERTY LOCATION ${output_device_file})
+
+    if (DEFINED output_target)
+        set(${output_target} prims-${device}-device PARENT_SCOPE)
+    endif()
+endfunction()
+
 function(generate_xc7_device_db)
     # ~~~
     # generate_xc7_device_db(
@@ -316,10 +392,16 @@ function(generate_nexus_device_db)
         output_target prjoxide_device
     )
 
-    # TODO: any patching that is needed
+    # Add primitive library
+    patch_device_with_prim_lib(
+        device ${device}
+        yosys_script synth_nexus
+        input_device ${prjoxide_device}
+        output_target prjoxide_prims_device
+    )
 
     if(DEFINED device_target)
-        set(${device_target} ${prjoxide_device} PARENT_SCOPE)
+        set(${device_target} ${prjoxide_prims_device} PARENT_SCOPE)
     endif()
 endfunction()
 

fpga_interchange/examples/tests.cmake

@@ -34,7 +34,7 @@ function(add_interchange_test)
     #   - test-fpga_interchange-<name>-phys     : interchange physical netlist
     #   - test-fpga_interchange-<name>-dcp     : design checkpoint with RapidWright
 
-    set(options)
+    set(options skip_dcp)
     set(oneValueArgs name family device package tcl xdc top techmap)
     set(multiValueArgs sources)
 
@@ -50,6 +50,7 @@ function(add_interchange_test)
     set(family ${add_interchange_test_family})
     set(device ${add_interchange_test_device})
     set(package ${add_interchange_test_package})
+    set(skip_dcp ${add_interchange_test_skip_dcp})
     set(top ${add_interchange_test_top})
     set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
     set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
@@ -246,6 +247,10 @@ function(add_interchange_test)
 
     add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml})
 
+    if(skip_dcp)
+        add_dependencies(all-${family}-tests test-${family}-${name}-phys-yaml)
+        add_dependencies(all-${device}-tests test-${family}-${name}-phys-yaml)
+    else()
         set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
         add_custom_command(
             OUTPUT ${dcp}
@@ -263,6 +268,7 @@ function(add_interchange_test)
         add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
         add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
         add_dependencies(all-${device}-tests test-${family}-${name}-dcp)
+    endif()
 endfunction()
 
 function(add_interchange_group_test)

fpga_interchange/examples/tests/CMakeLists.txt

@@ -4,3 +4,4 @@ add_subdirectory(counter)
 add_subdirectory(ram)
 add_subdirectory(ff)
 add_subdirectory(lut)
+add_subdirectory(lut_nexus)

fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt

@@ -0,0 +1,10 @@
+add_interchange_test(
+    name lut_nexus
+    family ${family}
+    device LIFCL-17
+    package QFN72
+    tcl run.tcl
+    xdc empty.xdc
+    sources lut.v
+    skip_dcp
+)

fpga_interchange/examples/tests/lut_nexus/lut.v

@@ -0,0 +1,7 @@
+module top;
+	wire x, y;
+	(*keep*)
+	LUT4 lut_0(.A(x), .B(x), .C(x), .D(x), .Z(y));
+	(*keep*)
+	LUT4 lut_1(.A(y), .B(y), .C(y), .D(y), .Z(x));
+endmodule

fpga_interchange/examples/tests/lut_nexus/run.tcl

@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_nexus -noccu2 -nobram -nolutram -nowidelut
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)