Merge pull request #340 from YosysHQ/dave/ecp5_io
ecp5: IOLOGIC improvements
This commit is contained in:
David Shah
GitHub
commit
ee769420e3
@ -119,7 +119,16 @@ inline const NetInfo *get_net_or_empty(const CellInfo *cell, const IdString port
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return found->second.net;
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else
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return nullptr;
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};
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}
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inline NetInfo *get_net_or_empty(CellInfo *cell, const IdString port)
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{
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auto found = cell->ports.find(port);
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if (found != cell->ports.end())
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return found->second.net;
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else
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return nullptr;
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}
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NEXTPNR_NAMESPACE_END
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@ -889,6 +889,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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if (cell->ports.at(port).name == id_STOP)
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return TMG_ENDPOINT;
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return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
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} else if (cell->type == id_ECLKBRIDGECS) {
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if (cell->ports.at(port).name == id_SEL)
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return TMG_ENDPOINT;
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return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
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} else {
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log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
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cell->name.c_str(this));
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@ -888,9 +888,15 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
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std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
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if (datamux_oddr != "PADDO")
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cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
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std::string datamux_oreg = str_or_default(ci->params, ctx->id("DATAMUX_OREG"), "PADDO");
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if (datamux_oreg != "PADDO")
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cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
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std::string datamux_mddr = str_or_default(ci->params, ctx->id("DATAMUX_MDDR"), "PADDO");
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if (datamux_mddr != "PADDO")
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cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
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std::string trimux_tsreg = str_or_default(ci->params, ctx->id("TRIMUX_TSREG"), "PADDT");
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if (trimux_tsreg != "PADDT")
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cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
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} else if (ci->type == ctx->id("DCCA")) {
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const NetInfo *cen = get_net_or_empty(ci, ctx->id("CE"));
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if (cen != nullptr) {
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@ -1367,6 +1373,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
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std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
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if (get_net_or_empty(ci, id_STOP) != nullptr)
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cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
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} else if (ci->type == id_ECLKBRIDGECS) {
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Loc loc = ctx->getBelLocation(ci->bel);
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bool r = loc.x > 5;
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std::string eclkb = ctx->locInfo(bel)->bel_data[bel.index].name.get();
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std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
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if (get_net_or_empty(ci, id_STOP) != nullptr)
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cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
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} else if (ci->type == id_DDRDLL) {
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Loc loc = ctx->getBelLocation(ci->bel);
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bool u = loc.y<15, r = loc.x> 15;
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@ -1181,6 +1181,7 @@ X(RDPNTR2)
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X(WRPNTR0)
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X(WRPNTR1)
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X(WRPNTR2)
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X(SLIP)
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X(GSR)
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@ -1289,3 +1290,7 @@ X(MULT18X18D_REGS_NONE)
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X(MULT18X18D_REGS_OUTPUT)
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X(MULT18X18D_REGS_PIPELINE)
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X(P)
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X(ECLKBRIDGECS)
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X(SEL)
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X(ECSOUT)
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191
ecp5/pack.cc
191
ecp5/pack.cc
@ -1560,6 +1560,7 @@ class Ecp5Packer
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};
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std::map<std::pair<int, int>, EdgeClockInfo> eclks;
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std::map<NetInfo *, int> bridge_side_hint;
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void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank)
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{
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@ -1575,6 +1576,8 @@ class Ecp5Packer
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break;
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}
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} else if (free_eclk == -1) {
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if (bridge_side_hint.count(ecknet) && bridge_side_hint.at(ecknet) != i)
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continue;
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free_eclk = i;
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}
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}
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@ -1844,6 +1847,8 @@ class Ecp5Packer
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auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
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auto &curr_mode = iol->params[ctx->id("MODE")].str;
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if (curr_mode != "NONE" && mode == "IREG_OREG")
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return;
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if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode)
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log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(),
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mode.c_str());
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@ -2044,10 +2049,10 @@ class Ecp5Packer
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replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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packed_cells.insert(cell.first);
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} else if (ci->type == ctx->id("ODDRX2F")) {
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} else if (ci->type == ctx->id("ODDRX2F") || ci->type == ctx->id("ODDR71B")) {
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CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
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if (pio == nullptr)
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log_error("ODDRX2F '%s' Q output must be connected only to a top level output\n",
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log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
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ci->name.c_str(ctx));
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CellInfo *iol;
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if (pio_iologic.count(pio->name))
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@ -2070,14 +2075,25 @@ class Ecp5Packer
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replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
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replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
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replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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if (ci->type == ctx->id("ODDR71B")) {
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Loc loc =
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ctx->getBelLocation(ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string())));
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if (loc.z % 2 == 1)
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log_error("ODDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
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replace_port(ci, ctx->id("D4"), iol, id_TXDATA4);
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replace_port(ci, ctx->id("D5"), iol, id_TXDATA5);
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replace_port(ci, ctx->id("D6"), iol, id_TXDATA6);
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iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDR71");
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} else {
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iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDRX2");
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}
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
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packed_cells.insert(cell.first);
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} else if (ci->type == ctx->id("IDDRX2F")) {
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} else if (ci->type == ctx->id("IDDRX2F") || ci->type == ctx->id("IDDR71B")) {
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CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
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if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
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log_error("IDDRX2F '%s' D input must be connected only to a top level input\n",
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log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
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ci->name.c_str(ctx));
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CellInfo *iol;
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if (pio_iologic.count(pio->name))
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@ -2093,8 +2109,20 @@ class Ecp5Packer
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replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
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replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
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replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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if (ci->type == ctx->id("IDDR71B")) {
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Loc loc =
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ctx->getBelLocation(ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string())));
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if (loc.z % 2 == 1)
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log_error("IDDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
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replace_port(ci, ctx->id("Q4"), iol, id_RXDATA4);
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replace_port(ci, ctx->id("Q5"), iol, id_RXDATA5);
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replace_port(ci, ctx->id("Q6"), iol, id_RXDATA6);
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replace_port(ci, ctx->id("ALIGNWD"), iol, id_SLIP);
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iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDR71");
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} else {
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iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDRX2");
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}
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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packed_cells.insert(cell.first);
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} else if (ci->type == ctx->id("OSHX2A")) {
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CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
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@ -2217,9 +2245,148 @@ class Ecp5Packer
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std::string(ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270");
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iol->params[ctx->id("IOLTOMUX")] = std::string("TDDR");
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packed_cells.insert(cell.first);
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} else if (ci->type == ctx->id("TRELLIS_FF") && bool_or_default(ci->attrs, ctx->id("syn_useioff"))) {
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// Pack IO flipflop into IOLOGIC
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std::string mode = str_or_default(ci->attrs, ctx->id("ioff_dir"), "");
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if (mode != "output") {
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// See if it can be packed as an input ff
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NetInfo *d = get_net_or_empty(ci, ctx->id("DI"));
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CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
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if (pio != nullptr && d->users.size() == 1) {
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// Input FF
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CellInfo *iol;
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if (pio_iologic.count(pio->name))
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iol = pio_iologic.at(pio->name);
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else
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iol = create_pio_iologic(pio, ci);
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set_iologic_mode(iol, "IREG_OREG");
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set_iologic_sclk(iol, ci, ctx->id("CLK"), true);
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set_iologic_lsr(iol, ci, ctx->id("LSR"), true);
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// Handle CLK and CE muxes
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if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
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iol->params[ctx->id("CLKIMUX")] = std::string("INV");
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if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
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iol->params[ctx->id("CEIMUX")] = std::string("CEMUX");
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iol->params[ctx->id("CEMUX")] = std::string("CE");
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if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
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replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
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else
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disconnect_port(ctx, ci, ctx->id("CE"));
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} else {
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iol->params[ctx->id("CEIMUX")] = std::string("1");
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}
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// Set IOLOGIC params from FF params
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iol->params[ctx->id("FF.INREGMODE")] = std::string("FF");
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iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, ctx->id("REGSET"), "RESET");
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iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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replace_port(ci, ctx->id("DI"), iol, id_PADDI);
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replace_port(ci, ctx->id("Q"), iol, id_INFF);
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packed_cells.insert(cell.first);
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continue;
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}
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}
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if (mode != "input") {
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CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
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CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
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if (pio_t != nullptr || pio_i != nullptr) {
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// Output or tristate FF
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bool tri = (pio_t != nullptr);
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CellInfo *pio = tri ? pio_t : pio_i;
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CellInfo *iol;
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if (pio_iologic.count(pio->name))
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iol = pio_iologic.at(pio->name);
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else
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iol = create_pio_iologic(pio, ci);
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set_iologic_mode(iol, "IREG_OREG");
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// Connection between FF and PIO
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replace_port(ci, ctx->id("Q"), iol, tri ? id_IOLTO : id_IOLDO);
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if (tri) {
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if (!pio->ports.count(id_IOLTO)) {
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pio->ports[id_IOLTO].name = id_IOLTO;
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pio->ports[id_IOLTO].type = PORT_IN;
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}
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pio->params[ctx->id("TRIMUX_TSREG")] = std::string("IOLTO");
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replace_port(pio, id_T, pio, id_IOLTO);
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} else {
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if (!pio->ports.count(id_IOLDO)) {
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pio->ports[id_IOLDO].name = id_IOLDO;
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pio->ports[id_IOLDO].type = PORT_IN;
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}
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pio->params[ctx->id("DATAMUX_OREG")] = std::string("IOLDO");
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replace_port(pio, id_I, pio, id_IOLDO);
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}
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set_iologic_sclk(iol, ci, ctx->id("CLK"), false);
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set_iologic_lsr(iol, ci, ctx->id("LSR"), false);
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// Handle CLK and CE muxes
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if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
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iol->params[ctx->id("CLKOMUX")] = std::string("INV");
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if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
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iol->params[ctx->id("CEOMUX")] = std::string("CEMUX");
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iol->params[ctx->id("CEMUX")] = std::string("CE");
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if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
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replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
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else
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disconnect_port(ctx, ci, ctx->id("CE"));
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} else {
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iol->params[ctx->id("CEOMUX")] = std::string("1");
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}
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// FF params
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iol->params[ctx->id(tri ? "TSREG.OUTREGMODE" : "OUTREG.OUTREGMODE")] = std::string("FF");
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iol->params[ctx->id(tri ? "TSREG.REGSET" : "OUTREG.REGSET")] =
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str_or_default(ci->params, ctx->id("REGSET"), "RESET");
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iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
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// Data input
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replace_port(ci, ctx->id("DI"), iol, tri ? id_TSDATA0 : id_TXDATA0);
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iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
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packed_cells.insert(cell.first);
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continue;
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}
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}
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log_error("Failed to pack flipflop '%s' with 'syn_useioff' set into IOLOGIC.\n", ci->name.c_str(ctx));
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}
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}
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flush_cells();
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// Constrain ECLK-related cells
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == id_ECLKBRIDGECS) {
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NetInfo *i0 = get_net_or_empty(ci, id_CLK0), *i1 = get_net_or_empty(ci, id_CLK1),
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*o = get_net_or_empty(ci, id_ECSOUT);
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for (NetInfo *input : {i0, i1}) {
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if (input == nullptr)
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continue;
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for (auto user : input->users) {
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if (!user.cell->attrs.count(ctx->id("BEL")))
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continue;
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Loc user_loc = ctx->getBelLocation(
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ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")).as_string())));
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for (auto bel : ctx->getBels()) {
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if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
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continue;
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Loc loc = ctx->getBelLocation(bel);
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if (loc.x == user_loc.x) {
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ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
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if (o != nullptr)
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for (auto user2 : o->users) {
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// Set side hint to ensure edge clock choice is routeable
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if (user2.cell->type == id_ECLKSYNCB && user2.port == id_ECLKI) {
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NetInfo *synco = get_net_or_empty(user2.cell, id_ECLKO);
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if (synco != nullptr)
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bridge_side_hint[synco] = (loc.x > 1) ? 0 : 1;
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}
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}
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goto eclkbridge_done;
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}
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}
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}
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}
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eclkbridge_done:
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continue;
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}
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}
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// Promote/route edge clocks
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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@ -2240,7 +2407,6 @@ class Ecp5Packer
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}
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}
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flush_cells();
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// Constrain ECLK-related cells
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for (auto cell : sorted(ctx->cells)) {
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CellInfo *ci = cell.second;
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if (ci->type == id_CLKDIVF) {
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@ -2266,7 +2432,18 @@ class Ecp5Packer
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clkdiv_done:
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continue;
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} else if (ci->type == id_ECLKSYNCB) {
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const NetInfo *eclki = net_or_nullptr(ci, id_ECLKI);
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const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
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if (eclki != nullptr && eclki->driver.cell != nullptr) {
|
||||
if (eclki->driver.cell->type == id_ECLKBRIDGECS) {
|
||||
BelId bel =
|
||||
ctx->getBelByName(ctx->id(eclki->driver.cell->attrs.at(ctx->id("BEL")).as_string()));
|
||||
Loc loc = ctx->getBelLocation(bel);
|
||||
ci->attrs[ctx->id("BEL")] =
|
||||
ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
|
||||
goto eclksync_done;
|
||||
}
|
||||
}
|
||||
if (eclko == nullptr)
|
||||
log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
|
||||
for (auto user : eclko->users) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user