Add LUT bypass to improve routability
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@ -373,6 +373,9 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
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# DFF bypass
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by = tt.create_pip(f"{name}.DI",f"{name}.DO","BYPASS")
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by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
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# LUT bypass
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by = tt.create_pip(f"{name}.I1",f"{name}.LO","BYPASS")
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by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
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elif (tile_type.startswith("TILE") and bel=="CY"):
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# matrix of each input to each output combination
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# crossbar but use mux placeholder for convenience
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@ -120,7 +120,7 @@ void NgUltraImpl::postRoute()
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ctx->assignArchInfo();
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log_break();
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log_info("Resources spent on routing:\n");
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int dff_bypass = 0, fe_new = 0, wfg_bypass = 0, gck_bypass = 0;
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int dff_bypass = 0, lut_bypass = 0, fe_new = 0, wfg_bypass = 0, gck_bypass = 0;
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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for (auto &w : ni->wires) {
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@ -140,10 +140,16 @@ void NgUltraImpl::postRoute()
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CellInfo *cell = ctx->getBoundBelCell(bel);
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switch(type.index) {
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case id_BEYOND_FE.index :
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if (extra_data.input==0) {
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dff_bypass++;
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// set bypass mode for DFF
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cell->setParam(ctx->id("type"), Property("BFF"));
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cell->params[id_dff_used] = Property(1,1);
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} else {
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lut_bypass++;
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cell->params[id_lut_used] = Property(1,1);
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cell->params[id_lut_table] = Property(0xaaaa, 16);
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}
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break;
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case id_WFG.index : wfg_bypass++;
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cell->setParam(ctx->id("type"), Property("WFB"));
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@ -156,7 +162,9 @@ void NgUltraImpl::postRoute()
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}
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}
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}
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log_info(" %6d DFFs used as BFF (%d new allocated FEs)\n", dff_bypass, fe_new);
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log_info(" %6d DFFs used in bypass mode (BFF)\n", dff_bypass);
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log_info(" %6d LUTs used in bypass mode\n", lut_bypass);
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log_info(" %6d newly allocated FEs\n", fe_new);
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log_info(" %6d WFGs used as WFB\n", wfg_bypass);
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log_info(" %6d GCK\n", gck_bypass);
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