Add LUT bypass to improve routability

This commit is contained in:
Miodrag Milanovic 2024-05-10 12:58:22 +02:00
parent e8a1b51eec
commit eef97d5e73
2 changed files with 17 additions and 6 deletions

View File

@ -373,6 +373,9 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
# DFF bypass
by = tt.create_pip(f"{name}.DI",f"{name}.DO","BYPASS")
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,0,0)
# LUT bypass
by = tt.create_pip(f"{name}.I1",f"{name}.LO","BYPASS")
by.extra_data = PipExtraData(ch.strs.id(name),PIP_EXTRA_BYPASS,1,0)
elif (tile_type.startswith("TILE") and bel=="CY"):
# matrix of each input to each output combination
# crossbar but use mux placeholder for convenience

View File

@ -120,7 +120,7 @@ void NgUltraImpl::postRoute()
ctx->assignArchInfo();
log_break();
log_info("Resources spent on routing:\n");
int dff_bypass = 0, fe_new = 0, wfg_bypass = 0, gck_bypass = 0;
int dff_bypass = 0, lut_bypass = 0, fe_new = 0, wfg_bypass = 0, gck_bypass = 0;
for (auto &net : ctx->nets) {
NetInfo *ni = net.second.get();
for (auto &w : ni->wires) {
@ -140,10 +140,16 @@ void NgUltraImpl::postRoute()
CellInfo *cell = ctx->getBoundBelCell(bel);
switch(type.index) {
case id_BEYOND_FE.index :
if (extra_data.input==0) {
dff_bypass++;
// set bypass mode for DFF
cell->setParam(ctx->id("type"), Property("BFF"));
cell->params[id_dff_used] = Property(1,1);
} else {
lut_bypass++;
cell->params[id_lut_used] = Property(1,1);
cell->params[id_lut_table] = Property(0xaaaa, 16);
}
break;
case id_WFG.index : wfg_bypass++;
cell->setParam(ctx->id("type"), Property("WFB"));
@ -156,7 +162,9 @@ void NgUltraImpl::postRoute()
}
}
}
log_info(" %6d DFFs used as BFF (%d new allocated FEs)\n", dff_bypass, fe_new);
log_info(" %6d DFFs used in bypass mode (BFF)\n", dff_bypass);
log_info(" %6d LUTs used in bypass mode\n", lut_bypass);
log_info(" %6d newly allocated FEs\n", fe_new);
log_info(" %6d WFGs used as WFB\n", wfg_bypass);
log_info(" %6d GCK\n", gck_bypass);