Progress with chipdb refactoring
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
ad0df6cea8
commit
f0edb625e3
@ -153,7 +153,7 @@ BelId Chip::getBelByName(IdString name) const
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if (bel_by_name.empty()) {
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for (int i = 0; i < chip_info.num_bels; i++)
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bel_by_name[chip_info.bel_data[i].name] = i;
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bel_by_name[chip_info.bel_data[i].name.ptr()] = i;
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}
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auto it = bel_by_name.find(name);
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@ -190,7 +190,7 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
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assert(bel != BelId());
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int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires;
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BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires;
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BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.ptr();
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for (int i = 0; i < num_bel_wires; i++)
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if (bel_wires[i].port == pin) {
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45
ice40/chip.h
45
ice40/chip.h
@ -72,7 +72,6 @@ PortPin portPinFromId(IdString id);
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// -----------------------------------------------------------------------
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#if 0
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template <typename T>
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struct RelPtr {
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int offset;
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@ -87,16 +86,17 @@ struct RelPtr {
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T*operator->() {
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return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
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}
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T*ptr() {
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return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
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}
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};
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#else
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template <typename T> using RelPtr = T *;
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#endif
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struct BelWirePOD
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{
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int32_t wire_index;
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PortPin port;
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};
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} __attribute__((packed));
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struct BelInfoPOD
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{
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@ -105,13 +105,14 @@ struct BelInfoPOD
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int32_t num_bel_wires;
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RelPtr<BelWirePOD> bel_wires;
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int8_t x, y, z;
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};
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int8_t filler_0;
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} __attribute__((packed));
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struct BelPortPOD
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{
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int32_t bel_index;
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PortPin port;
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};
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} __attribute__((packed));
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struct PipInfoPOD
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{
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@ -120,33 +121,33 @@ struct PipInfoPOD
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int8_t x, y;
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int16_t switch_mask;
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int32_t switch_index;
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};
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} __attribute__((packed));
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struct WireInfoPOD
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{
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RelPtr<char> name;
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const char *name;
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int32_t num_uphill, num_downhill;
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RelPtr<int32_t> pips_uphill, pips_downhill;
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int32_t *pips_uphill, *pips_downhill;
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int32_t num_bels_downhill;
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BelPortPOD bel_uphill;
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RelPtr<BelPortPOD> bels_downhill;
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BelPortPOD *bels_downhill;
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int8_t x, y;
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};
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} __attribute__((packed));
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struct PackagePinPOD
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{
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const char *name;
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int32_t bel_index;
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};
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} __attribute__((packed));
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struct PackageInfoPOD
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{
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const char *name;
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int num_pins;
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PackagePinPOD *pins;
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};
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} __attribute__((packed));
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enum TileType
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{
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@ -160,21 +161,21 @@ enum TileType
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struct ConfigBitPOD
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{
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int8_t row, col;
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};
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} __attribute__((packed));
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struct ConfigEntryPOD
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{
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const char *name;
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int num_bits;
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ConfigBitPOD *bits;
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};
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} __attribute__((packed));
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struct TileInfoPOD
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{
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int8_t cols, rows;
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int num_config_entries;
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ConfigEntryPOD *entries;
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};
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} __attribute__((packed));
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static const int max_switch_bits = 5;
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@ -183,13 +184,13 @@ struct SwitchInfoPOD
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int8_t x, y;
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int num_bits;
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ConfigBitPOD cbits[max_switch_bits];
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};
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} __attribute__((packed));
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struct IerenInfoPOD
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{
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int8_t iox, ioy, ioz;
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int8_t ierx, iery, ierz;
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};
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} __attribute__((packed));
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struct BitstreamInfoPOD
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{
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@ -197,7 +198,7 @@ struct BitstreamInfoPOD
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TileInfoPOD *tiles_nonrouting;
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SwitchInfoPOD *switches;
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IerenInfoPOD *ierens;
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};
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} __attribute__((packed));
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struct ChipInfoPOD
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{
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@ -210,7 +211,7 @@ struct ChipInfoPOD
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TileType *tile_grid;
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BitstreamInfoPOD *bits_info;
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PackageInfoPOD *packages_data;
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};
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} __attribute__((packed));
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extern ChipInfoPOD chip_info_384;
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extern ChipInfoPOD chip_info_1k;
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@ -476,7 +477,7 @@ struct Chip
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IdString getBelName(BelId bel) const
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{
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assert(bel != BelId());
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return chip_info.bel_data[bel.index].name;
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return chip_info.bel_data[bel.index].name.ptr();
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}
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void bindBel(BelId bel, IdString cell)
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159
ice40/chipdb.py
159
ice40/chipdb.py
@ -4,6 +4,8 @@ import sys
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import re
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import textwrap
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endianness = "le"
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dev_name = None
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dev_width = None
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dev_height = None
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@ -39,6 +41,25 @@ tile_bits = [[] for _ in range(num_tile_types)]
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cbit_re = re.compile(r'B(\d+)\[(\d+)\]')
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portpins = dict()
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beltypes = dict()
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with open("ice40/portpins.inc") as f:
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for line in f:
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line = line.replace("(", " ")
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line = line.replace(")", " ")
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line = line.split()
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if len(line) == 0:
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continue
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assert len(line) == 2
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assert line[0] == "X"
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idx = len(portpins) + 1
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portpins[line[1]] = idx
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beltypes["ICESTORM_LC"] = 1
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beltypes["ICESTORM_RAM"] = 2
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beltypes["SB_IO"] = 3
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beltypes["SB_GB"] = 4
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def maj_wire_name(name):
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if re.match(r"lutff_\d/(in|out)", name[2]):
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@ -344,24 +365,144 @@ elif dev_name == "384":
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add_bel_gb( 3, 0, 5)
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add_bel_gb( 3, 9, 4)
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class BinaryBlobAssembler:
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def __init__(self):
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self.data = bytearray()
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self.comments = dict()
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self.labels = dict()
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self.labels_byaddr = dict()
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self.ltypes_byaddr = dict()
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self.refs = dict()
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def l(self, name, ltype = None):
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assert name not in self.labels
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assert len(self.data) not in self.labels_byaddr
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self.labels[name] = len(self.data)
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if ltype is not None:
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self.ltypes_byaddr[len(self.data)] = ltype
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self.labels_byaddr[len(self.data)] = name
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def r(self, name, comment):
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assert len(self.data) not in self.refs
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self.refs[len(self.data)] = (name, comment)
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self.data.append(0)
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self.data.append(0)
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self.data.append(0)
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self.data.append(0)
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def s(self, v, comment):
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for i in range(len(v)):
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self.data.append(ord(v[i]))
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self.data.append(0)
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self.comments[len(self.data)] = comment
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def u8(self, v, comment):
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self.data.append(v)
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self.comments[len(self.data)] = comment
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def u16(self, v, comment):
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if endianness == "le":
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self.data.append(v & 255)
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self.data.append((v >> 8) & 255)
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elif endianness == "be":
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self.data.append((v >> 8) & 255)
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self.data.append(v & 255)
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else:
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assert 0
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self.comments[len(self.data)] = comment
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def u32(self, v, comment):
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if endianness == "le":
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self.data.append(v & 255)
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self.data.append((v >> 8) & 255)
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self.data.append((v >> 16) & 255)
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self.data.append((v >> 24) & 255)
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elif endianness == "be":
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self.data.append((v >> 24) & 255)
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self.data.append((v >> 16) & 255)
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self.data.append((v >> 8) & 255)
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self.data.append(v & 255)
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else:
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assert 0
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self.comments[len(self.data)] = comment
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def write_c(self, f):
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cursor = 0
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bytecnt = 0
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while cursor < len(self.data):
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if cursor in self.comments:
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if bytecnt == 0:
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print(" ", end="")
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print(" // %s" % self.comments[cursor])
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bytecnt = 0
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if cursor in self.labels_byaddr:
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if bytecnt != 0:
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print()
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if cursor in self.ltypes_byaddr:
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print("#define %s ((%s*)(binblob_%s+%d))" % (self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], dev_name, cursor))
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else:
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print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]))
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bytecnt = 0
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if cursor in self.refs:
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v = self.labels[self.refs[cursor][0]] - cursor
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if bytecnt != 0:
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print()
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print(" ", end="")
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if endianness == "le":
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print(" %3d," % (v & 255), end="")
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print(" %3d," % ((v >> 8) & 255), end="")
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print(" %3d," % ((v >> 16) & 255), end="")
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print(" %3d," % ((v >> 24) & 255), end="")
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elif endianness == "be":
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print(" %3d," % (v & 255), end="")
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print(" %3d," % ((v >> 8) & 255), end="")
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print(" %3d," % ((v >> 16) & 255), end="")
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print(" %3d," % ((v >> 24) & 255), end="")
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else:
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assert 0
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print(" // [%d] %s (reference to %s)" % (cursor, self.refs[cursor][1], self.refs[cursor][0]))
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bytecnt = 0
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cursor += 4
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else:
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if bytecnt == 0:
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print(" ", end="")
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print(" %3d," % self.data[cursor], end=("" if bytecnt < 15 else "\n"))
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bytecnt = (bytecnt + 1) & 15
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cursor += 1
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if bytecnt != 0:
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print()
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bba = BinaryBlobAssembler()
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print('#include "nextpnr.h"')
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print('namespace {')
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print('USING_NEXTPNR_NAMESPACE')
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index = 0
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print("static BelWirePOD bel_wires[] = {")
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for bel in range(len(bel_name)):
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print("#define bel_wires_%d (bel_wires+%d)" % (bel, index))
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bba.l("bel_wires_%d" % bel, "BelWirePOD")
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for i in range(len(bel_wires[bel])):
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print(" {%d, PIN_%s}," % bel_wires[bel][i])
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bba.u32(bel_wires[bel][i][0], "wire_index")
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bba.u32(portpins[bel_wires[bel][i][1]], "port")
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index += 1
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print("};")
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print("static BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
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for bel in range(len(bel_name)):
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print(" {\"%s\", TYPE_%s, %d, bel_wires_%d, %d, %d, %d}%s" % (bel_name[bel], bel_type[bel],
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len(bel_wires[bel]), bel, bel_pos[bel][0], bel_pos[bel][1], bel_pos[bel][2],
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"," if bel+1 < len(bel_name) else ""))
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bba.l("bel_name_%d" % bel, "char")
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bba.s(bel_name[bel], "name: %s" % bel_name[bel])
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bba.l("bel_data", "BelInfoPOD")
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for bel in range(len(bel_name)):
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bba.r("bel_name_%d" % bel, "name")
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bba.u32(beltypes[bel_type[bel]], "type")
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bba.u32(len(bel_wires[bel]), "num_bel_wires")
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bba.r("bel_wires_%d" % bel, "bel_wires")
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bba.u8(bel_pos[bel][0], "x")
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bba.u8(bel_pos[bel][1], "y")
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bba.u8(bel_pos[bel][2], "z")
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bba.u8(0, "filler")
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print("static uint8_t binblob_%s[] = {" % dev_name)
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bba.write_c(sys.stdout)
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print("};")
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wireinfo = list()
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@ -540,7 +681,7 @@ print('NEXTPNR_NAMESPACE_BEGIN')
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print("ChipInfoPOD chip_info_%s = {" % dev_name)
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print(" %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
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print(" bel_data_%s, wire_data_%s, pip_data_%s," % (dev_name, dev_name, dev_name))
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print(" bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
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print(" tile_grid_%s, &bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
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print("};")
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