caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge pull request #628 from acomodi/add-interchange-devices

Browse Source 
fpga_interchange: add more devices
This commit is contained in:
gatecat 2021-03-25 16:03:22 +00:00 committed by GitHub
commit f233bee970
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
22 changed files with 449 additions and 167 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
.github/ci/build_interchange.sh vendored
View File

@ -1,48 +1,52 @@
#!/bin/bash
# Install capnproto libraries
curl -O https://capnproto.org/capnproto-c++-0.8.0.tar.gz
tar zxf capnproto-c++-0.8.0.tar.gz
pushd capnproto-c++-0.8.0
./configure
make -j`nproc` check
sudo make install
popd
function build_capnp {
curl -O https://capnproto.org/capnproto-c++-0.8.0.tar.gz
tar zxf capnproto-c++-0.8.0.tar.gz
pushd capnproto-c++-0.8.0
./configure
make -j`nproc` check
sudo make install
popd
git clone https://github.com/capnproto/capnproto-java.git
pushd capnproto-java
make -j`nproc`
sudo make install
popd
}
# Install latest Yosys
git clone https://github.com/YosysHQ/yosys.git
pushd yosys
make -j`nproc`
sudo make install
popd
# Install capnproto java
git clone https://github.com/capnproto/capnproto-java.git
pushd capnproto-java
make
sudo make install
popd
RAPIDWRIGHT_PATH="`pwd`/RapidWright"
INTERCHANGE_SCHEMA_PATH="`pwd`/3rdparty/fpga-interchange-schema/interchange"
PYTHON_INTERCHANGE_PATH="`pwd`/python-fpga-interchange"
PYTHON_INTERCHANGE_TAG="v0.0.4"
# Install python-fpga-interchange libraries
git clone -b $PYTHON_INTERCHANGE_TAG https://github.com/SymbiFlow/python-fpga-interchange.git $PYTHON_INTERCHANGE_PATH
pushd $PYTHON_INTERCHANGE_PATH
git submodule update --init --recursive
python3 -m pip install -r requirements.txt
popd
# Install RapidWright
git clone https://github.com/Xilinx/RapidWright.git $RAPIDWRIGHT_PATH
pushd $RAPIDWRIGHT_PATH
make update_jars
popd
function build_yosys {
git clone https://github.com/YosysHQ/yosys.git
pushd yosys
make -j`nproc`
sudo make install
popd
}
mkdir build
pushd build
cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=$RAPIDWRIGHT_PATH -DINTERCHANGE_SCHEMA_PATH=$INTERCHANGE_SCHEMA_PATH -DPYTHON_INTERCHANGE_PATH=$PYTHON_INTERCHANGE_PATH
popd
function get_dependencies {
# Install python-fpga-interchange libraries
git clone -b ${PYTHON_INTERCHANGE_TAG} https://github.com/SymbiFlow/python-fpga-interchange.git ${PYTHON_INTERCHANGE_PATH}
pushd ${PYTHON_INTERCHANGE_PATH}
git submodule update --init --recursive
python3 -m pip install -r requirements.txt
popd
## Install RapidWright
git clone https://github.com/Xilinx/RapidWright.git ${RAPIDWRIGHT_PATH}
pushd ${RAPIDWRIGHT_PATH}
make update_jars
popd
}
function build_nextpnr {
build_capnp
mkdir build
pushd build
cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH} -DINTERCHANGE_SCHEMA_PATH=${INTERCHANGE_SCHEMA_PATH} -DPYTHON_INTERCHANGE_PATH=${PYTHON_INTERCHANGE_PATH}
make nextpnr-fpga_interchange -j`nproc`
popd
}

78
.github/workflows/interchange_ci.yml vendored
View File

@ -3,8 +3,7 @@ name: FPGA interchange CI tests
on: [push, pull_request]
jobs:
Run-tests:
Build-yosys:
runs-on: ubuntu-latest
steps:
@ -19,11 +18,78 @@ jobs:
sudo apt-get update
sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
- name: Execute build script
run: stdbuf -i0 -o0 -e0 ./.github/ci/build_interchange.sh
- name: ccache
uses: hendrikmuhs/ccache-action@v1
- name: Execute build yosys script
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source ./.github/ci/build_interchange.sh
build_yosys
Build-nextpnr:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
submodules: recursive
- uses: actions/setup-python@v2
- name: Install
run: |
sudo apt-get update
sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
- name: ccache
uses: hendrikmuhs/ccache-action@v1
- name: Execute build interchange script
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source ./.github/ci/build_interchange.sh
build_nextpnr
Run-Tests:
runs-on: ubuntu-latest
needs: [Build-yosys, Build-nextpnr]
strategy:
matrix:
device: [xc7a35t, xc7a100t, xc7a200t, xc7z010]
steps:
- uses: actions/checkout@v2
with:
submodules: recursive
- uses: actions/setup-python@v2
- name: Install
run: |
sudo apt-get update
sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
- name: ccache
uses: hendrikmuhs/ccache-action@v1
- name: Execute build interchange script
env:
RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
INTERCHANGE_SCHEMA_PATH: ${{ github.workspace }}/3rdparty/fpga-interchange-schema/interchange
PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
PYTHON_INTERCHANGE_TAG: v0.0.4
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"
source ./.github/ci/build_interchange.sh
build_yosys && build_nextpnr && get_dependencies
- name: Run tests
env:
DEVICE: ${{ matrix.device }}
run: |
cd build
make all-fpga_interchange-archcheck-tests -j`nproc`
make all-fpga_interchange-tests -j`nproc`
make chipdb-$DEVICE-bin-check-test-data
make chipdb-$DEVICE-bin-check
make all-$DEVICE-tests -j`nproc`

45
fpga_interchange/examples/boards.cmake Normal file
View File

@ -0,0 +1,45 @@
function(add_board)
# ~~~
# add_board(
# name <board name>
# device <common device>
# package <package>
# )
# ~~~
#
# Generates a board target containing information on the common device and package
# of the board.
#
# Arguments:
# - name: name of the board. E.g. arty
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
# share the same xc7a35t device prefix
# - package: one of the packages available for a given device. E.g. cpg236
#
# Targets generated:
# - board-<name>
set(options)
set(oneValueArgs name device package)
set(multiValueArgs)
cmake_parse_arguments(
add_board
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
set(name ${add_board_name})
set(device ${add_board_device})
set(package ${add_board_package})
add_custom_target(board-${name} DEPENDS device-${device})
set_target_properties(
board-${name}
PROPERTIES
DEVICE ${device}
PACKAGE ${package}
)
endfunction()

29
fpga_interchange/examples/boards/CMakeLists.txt Normal file
View File

@ -0,0 +1,29 @@
add_board(
name arty35t
device xc7a35t
package csg324
)
add_board(
name arty100t
device xc7a100t
package csg324
)
add_board(
name nexys_video
device xc7a200t
package sbg484
)
add_board(
name basys3
device xc7a35t
package cpg236
)
add_board(
name zybo
device xc7z010
package clg400
)

7
fpga_interchange/examples/chipdb.cmake
View File

@ -41,7 +41,7 @@ function(create_rapidwright_device_db)
OUTPUT ${rapidwright_device_db}
COMMAND
RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
${INVOKE_RAPIDWRIGHT}
${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
com.xilinx.rapidwright.interchange.DeviceResourcesExample
${part}
DEPENDS
@ -367,6 +367,9 @@ function(generate_chipdb)
${CMAKE_CURRENT_SOURCE_DIR}
)
add_dependencies(all-${family}-archcheck-tests chipdb-${device}-bin-check-test-data chipdb-${device}-bin-check)
add_dependencies(all-${family}-archcheck-tests chipdb-${device}-bin-check-test-data chipdb-${device}-bin-check)
# All tests targets for this device are added to this target
add_custom_target(all-${device}-tests)
endfunction()

8
fpga_interchange/examples/common.mk
View File

@ -1,8 +0,0 @@
NEXTPNR_PATH := $(realpath ../../..)
NEXTPNR_BIN := $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange
BBA_PATH := $(realpath ..)/create_bba/build/xc7a35.bin
RAPIDWRIGHT_PATH := $(realpath ..)/create_bba/build/RapidWright
INTERCHANGE_PATH := $(realpath ..)/create_bba/build/fpga-interchange-schema/interchange
DEVICE := $(realpath ..)/create_bba/build/python-fpga-interchange/xc7a35tcpg236-1_constraints_luts.device

6
fpga_interchange/examples/devices/CMakeLists.txt
View File

@ -1 +1,7 @@
# Artix-7 devices
add_subdirectory(xc7a35t)
add_subdirectory(xc7a100t)
add_subdirectory(xc7a200t)
# Zynq-7 devices
add_subdirectory(xc7z010)

14
fpga_interchange/examples/devices/xc7a100t/CMakeLists.txt Normal file
View File

@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7a100t
part xc7a100tcsg324-1
device_target xc7a100t_target
)
generate_chipdb(
family ${family}
device xc7a100t
part xc7a100tcsg324-1
device_target ${xc7a100t_target}
device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
test_package csg324
)

36
fpga_interchange/examples/devices/xc7a100t/test_data.yaml Normal file
View File

@ -0,0 +1,36 @@
pip_test:
- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
dst_wire: SLICE_X15Y93.SLICEL/D3
pip_chain_test:
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
- INT_R_X3Y145/GND_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
- INT_R_X3Y145/VCC_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
- SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
- SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
bel_pin_test:
- bel: SLICE_X15Y93.SLICEL/D6LUT
pin: A3
wire: SLICE_X15Y93.SLICEL/D3
- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
pin: G
wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE

14
fpga_interchange/examples/devices/xc7a200t/CMakeLists.txt Normal file
View File

@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7a200t
part xc7a200tsbg484-1
device_target xc7a200t_target
)
generate_chipdb(
family ${family}
device xc7a200t
part xc7a200tsbg484-1
device_target ${xc7a200t_target}
device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
test_package sbg484
)

36
fpga_interchange/examples/devices/xc7a200t/test_data.yaml Normal file
View File

@ -0,0 +1,36 @@
pip_test:
- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
dst_wire: SLICE_X15Y93.SLICEL/D3
pip_chain_test:
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
- INT_R_X3Y145/GND_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
- TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
- INT_R_X3Y145/VCC_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
- SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
- SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
bel_pin_test:
- bel: SLICE_X15Y93.SLICEL/D6LUT
pin: A3
wire: SLICE_X15Y93.SLICEL/D3
- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
pin: G
wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE

14
fpga_interchange/examples/devices/xc7z010/CMakeLists.txt Normal file
View File

@ -0,0 +1,14 @@
generate_xc7_device_db(
device xc7z010
part xc7z010clg400-1
device_target xc7z010_target
)
generate_chipdb(
family ${family}
device xc7z010
part xc7z010clg400-1
device_target ${xc7z010_target}
device_config ${PYTHON_INTERCHANGE_PATH}/test_data/series7_device_config.yaml
test_package clg400
)

36
fpga_interchange/examples/devices/xc7z010/test_data.yaml Normal file
View File

@ -0,0 +1,36 @@
pip_test:
- src_wire: CLBLM_L_X8Y69/CLBLM_L_D3
dst_wire: SLICE_X11Y69.SLICEL/D3
pip_chain_test:
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE
- TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0
- INT_L_X8Y69/GND_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE
- TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1
- INT_L_X8Y69/VCC_WIRE
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
- $CONSTANTS_X0Y0/$VCC_NODE
- SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE
- SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1
- wires:
- $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- $CONSTANTS_X0Y0/$GND_NODE
- SLICE_X11Y69.SLICEL/$GND_SITE_WIRE
- SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0
bel_pin_test:
- bel: SLICE_X14Y63.SLICEL/D6LUT
pin: A3
wire: SLICE_X14Y63.SLICEL/D3
- bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
pin: G
wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE

91
fpga_interchange/examples/template.mk
View File

@ -1,91 +0,0 @@
include ../common.mk
.DELETE_ON_ERROR:
.PHONY: all debug clean netlist_yaml phys_yaml
all: build/$(DESIGN).dcp
build:
mkdir build
build/$(DESIGN).netlist: build/$(DESIGN).json
/usr/bin/time -v python3 -mfpga_interchange.yosys_json \
--schema_dir $(INTERCHANGE_PATH) \
--device $(DEVICE) \
--top $(DESIGN_TOP) \
build/$(DESIGN).json \
build/$(DESIGN).netlist
build/$(DESIGN)_netlist.yaml: build/$(DESIGN).netlist
/usr/bin/time -v python3 -mfpga_interchange.convert \
--schema_dir $(INTERCHANGE_PATH) \
--schema logical \
--input_format capnp \
--output_format yaml \
build/$(DESIGN).netlist \
build/$(DESIGN)_netlist.yaml
netlist_yaml: build/$(DESIGN)_netlist.yaml
build/$(DESIGN).phys: build/$(DESIGN).netlist
$(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--xdc $(DESIGN).xdc \
--netlist build/$(DESIGN).netlist \
--phys build/$(DESIGN).phys \
--package $(PACKAGE) \
build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
/usr/bin/time -v python3 -mfpga_interchange.convert \
--schema_dir $(INTERCHANGE_PATH) \
--schema physical \
--input_format capnp \
--output_format yaml \
build/$(DESIGN).phys \
build/$(DESIGN)_phys.yaml
phys_yaml: build/$(DESIGN)_phys.yaml
verbose: build/$(DESIGN).netlist
$(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--xdc $(DESIGN).xdc \
--netlist build/$(DESIGN).netlist \
--phys build/$(DESIGN).phys \
--package $(PACKAGE) \
--verbose
verbose2: build/$(DESIGN).netlist
$(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--xdc $(DESIGN).xdc \
--netlist build/$(DESIGN).netlist \
--phys build/$(DESIGN).phys \
--package $(PACKAGE) \
--debug
debug: build/$(DESIGN).netlist
gdb --args $(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--xdc $(DESIGN).xdc \
--netlist build/$(DESIGN).netlist \
--phys build/$(DESIGN).phys \
--package $(PACKAGE)
debug_verbose: build/$(DESIGN).netlist
gdb --args $(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
--xdc $(DESIGN).xdc \
--netlist build/$(DESIGN).netlist \
--phys build/$(DESIGN).phys \
--package $(PACKAGE) \
--verbose
build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp \
build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc build/$(DESIGN).dcp
clean:
rm -rf build

74
fpga_interchange/examples/tests.cmake
View File

@ -251,7 +251,7 @@ function(add_interchange_test)
OUTPUT ${dcp}
COMMAND
RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
${INVOKE_RAPIDWRIGHT}
${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
${netlist} ${phys} ${xdc} ${dcp}
DEPENDS
@ -262,4 +262,76 @@ function(add_interchange_test)
add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
add_dependencies(all-${device}-tests test-${family}-${name}-dcp)
endfunction()
function(add_interchange_group_test)
# ~~~
# add_interchange_group_test(
# name <name>
# family <family>
# board_list <boards>
# xdc_list <xdc>
# tcl <tcl>
# sources <sources list>
# [top <top name>]
# [techmap <techmap file>]
# )
#
# Generates targets to run desired tests over multiple devices.
#
# Arguments:
# - name: base test name. The real test name will be <name>_<board>
# - family: nextpnr architecture family (e.g. fpga_interchange)
# - board_list: list of boards, one for each test
# - tcl: tcl script used for synthesis
# - sources: list of HDL sources
# - top (optional): name of the top level module.
# If not provided, "top" is assigned as top level module
# - techmap (optional): techmap file used during synthesis
#
# This function internally calls add_interchange_test to generate the various tests.
#
# Note: it is assumed that there exists an XDC file for each board, with the following naming
# convention: <board>.xdc
set(options)
set(oneValueArgs name family tcl top techmap)
set(multiValueArgs sources board_list)
cmake_parse_arguments(
add_interchange_group_test
"${options}"
"${oneValueArgs}"
"${multiValueArgs}"
${ARGN}
)
set(name ${add_interchange_group_test_name})
set(family ${add_interchange_group_test_family})
set(top ${add_interchange_group_test_top})
set(tcl ${add_interchange_group_test_tcl})
set(techmap ${add_interchange_group_test_techmap})
set(sources ${add_interchange_group_test_sources})
if (NOT DEFINED top)
# Setting default top value
set(top "top")
endif()
foreach(board ${add_interchange_group_test_board_list})
get_property(device TARGET board-${board} PROPERTY DEVICE)
get_property(package TARGET board-${board} PROPERTY PACKAGE)
add_interchange_test(
name ${name}_${board}
family ${family}
device ${device}
package ${package}
tcl ${tcl}
xdc ${board}.xdc
sources ${sources}
top ${top}
)
endforeach()
endfunction()

18
fpga_interchange/examples/tests/wire/CMakeLists.txt
View File

@ -1,19 +1,7 @@
add_interchange_test(
name wire_basys3
add_interchange_group_test(
name wire
family ${family}
device xc7a35t
package cpg236
board_list basys3 arty35t zybo arty100t nexys_video
tcl run.tcl
xdc wire_basys3.xdc
sources wire.v
)
add_interchange_test(
name wire_arty
family ${family}
device xc7a35t
package csg324
tcl run.tcl
xdc wire_arty.xdc
sources wire.v
)

4
fpga_interchange/examples/tests/wire/wire_arty.xdc → fpga_interchange/examples/tests/wire/arty100t.xdc
View File

@ -1,5 +1,5 @@
set_property PACKAGE_PIN N16 [get_ports i]
set_property PACKAGE_PIN N15 [get_ports o]
set_property PACKAGE_PIN A8 [get_ports i]
set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

5
fpga_interchange/examples/tests/wire/arty35t.xdc Normal file
View File

@ -0,0 +1,5 @@
set_property PACKAGE_PIN A8 [get_ports i]
set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

0
fpga_interchange/examples/tests/wire/wire_basys3.xdc → fpga_interchange/examples/tests/wire/basys3.xdc
View File

5
fpga_interchange/examples/tests/wire/nexys_video.xdc Normal file
View File

@ -0,0 +1,5 @@
set_property PACKAGE_PIN E22 [get_ports i]
set_property PACKAGE_PIN T14 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

5
fpga_interchange/examples/tests/wire/zybo.xdc Normal file
View File

@ -0,0 +1,5 @@
set_property PACKAGE_PIN G15 [get_ports i]
set_property PACKAGE_PIN M14 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

5
fpga_interchange/family.cmake
View File

@ -6,7 +6,8 @@ endif()
find_package(ZLIB REQUIRED)
set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
set(INVOKE_RAPIDWRIGHT ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh CACHE PATH "Path to RapidWright invocation script")
set(INVOKE_RAPIDWRIGHT "${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh" CACHE PATH "Path to RapidWright invocation script")
set(JAVA_HEAP_SPACE "-Xmx8g" CACHE STRING "Heap space reserved for Java")
# FIXME: Make patch data available in the python package and remove this cached var
set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir")
@ -14,6 +15,7 @@ set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-sche
add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
include(${family}/examples/chipdb.cmake)
include(${family}/examples/boards.cmake)
include(${family}/examples/tests.cmake)
set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
@ -22,6 +24,7 @@ file(MAKE_DIRECTORY ${chipdb_dir})
add_custom_target(all-${family}-tests)
add_custom_target(all-${family}-archcheck-tests)
add_subdirectory(${family}/examples/devices)
add_subdirectory(${family}/examples/boards)
add_subdirectory(${family}/examples/tests)
set(PROTOS lookahead.capnp)