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sdf: Working on support for CVC

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-10-24 12:37:07 +01:00
parent 8343488bdf
commit f2b9cc6d23
4 changed files with 20 additions and 8 deletions
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3
common/command.cc
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@ -150,6 +150,7 @@ po::options_description CommandHandler::getGeneralOptions()
general.add_options()("timing-allow-fail", "allow timing to fail in design"); general.add_options()("timing-allow-fail", "allow timing to fail in design");
general.add_options()("no-tmdriv", "disable timing-driven placement"); general.add_options()("no-tmdriv", "disable timing-driven placement");
general.add_options()("sdf", po::value<std::string>(), "SDF delay back-annotation file to write"); general.add_options()("sdf", po::value<std::string>(), "SDF delay back-annotation file to write");
general.add_options()("sdf-cvc", "enable tweaks for SDF file compatibility with the CVC simulator");
return general; return general;
} }
@ -343,7 +344,7 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx)
std::ofstream f(filename); std::ofstream f(filename);
if (!f) if (!f)
log_error("Failed to open SDF file '%s' for writing.\n", filename.c_str()); log_error("Failed to open SDF file '%s' for writing.\n", filename.c_str());
ctx->writeSDF(f); ctx->writeSDF(f, vm.count("sdf-cvc"));
} }
#ifndef NO_PYTHON #ifndef NO_PYTHON

2
common/nextpnr.h
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@ -809,7 +809,7 @@ struct Context : Arch, DeterministicRNG
// -------------------------------------------------------------- // --------------------------------------------------------------
// provided by sdf.cc // provided by sdf.cc
void writeSDF(std::ostream &out) const; void writeSDF(std::ostream &out, bool cvc_mode = false) const;
// -------------------------------------------------------------- // --------------------------------------------------------------

21
common/sdf.cc
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@ -78,6 +78,7 @@ struct Interconnect
struct SDFWriter struct SDFWriter
{ {
bool cvc_mode = false;
std::vector<Cell> cells; std::vector<Cell> cells;
std::vector<Interconnect> conn; std::vector<Interconnect> conn;
std::string sdfversion, design, vendor, program; std::string sdfversion, design, vendor, program;
@ -98,7 +99,7 @@ struct SDFWriter
{ {
std::string esc; std::string esc;
for (char c : name) { for (char c : name) {
if (c == '$' || c == '\\' || c == '[' || c == ']' || c == ':') if (c == '$' || c == '\\' || c == '[' || c == ']' || c == ':' || (cvc_mode && c == '.'))
esc += '\\'; esc += '\\';
esc += c; esc += c;
} }
@ -128,10 +129,19 @@ struct SDFWriter
void write_delay(std::ostream &out, const MinMaxTyp &delay) void write_delay(std::ostream &out, const MinMaxTyp &delay)
{ {
out << "(" << delay.min << ":" << delay.typ << ":" << delay.max << ")"; if (cvc_mode)
out << "(" << int(delay.min) << ":" << int(delay.typ) << ":" << int(delay.max) << ")";
else
out << "(" << delay.min << ":" << delay.typ << ":" << delay.max << ")";
} }
void write_port(std::ostream &out, const CellPort &port) { out << escape_name(port.cell + "/" + port.port); } void write_port(std::ostream &out, const CellPort &port)
{
if (cvc_mode)
out << escape_name(port.cell) + "." + escape_name(port.port);
else
out << escape_name(port.cell + "/" + port.port);
}
void write_portedge(std::ostream &out, const PortAndEdge &pe) void write_portedge(std::ostream &out, const PortAndEdge &pe)
{ {
@ -146,7 +156,7 @@ struct SDFWriter
out << " (DESIGN " << format_name(design) << ")" << std::endl; out << " (DESIGN " << format_name(design) << ")" << std::endl;
out << " (VENDOR " << format_name(vendor) << ")" << std::endl; out << " (VENDOR " << format_name(vendor) << ")" << std::endl;
out << " (PROGRAM " << format_name(program) << ")" << std::endl; out << " (PROGRAM " << format_name(program) << ")" << std::endl;
out << " (DIVIDER /)" << std::endl; out << " (DIVIDER " << (cvc_mode ? "." : "/") << ")" << std::endl;
out << " (TIMESCALE 1ps)" << std::endl; out << " (TIMESCALE 1ps)" << std::endl;
// Write interconnect delays, with the main design begin a "cell" // Write interconnect delays, with the main design begin a "cell"
out << " (CELL" << std::endl; out << " (CELL" << std::endl;
@ -210,10 +220,11 @@ struct SDFWriter
} // namespace SDF } // namespace SDF
void Context::writeSDF(std::ostream &out) const void Context::writeSDF(std::ostream &out, bool cvc_mode) const
{ {
using namespace SDF; using namespace SDF;
SDFWriter wr; SDFWriter wr;
wr.cvc_mode = cvc_mode;
wr.design = str_or_default(attrs, id("module"), "top"); wr.design = str_or_default(attrs, id("module"), "top");
wr.sdfversion = "3.0"; wr.sdfversion = "3.0";
wr.vendor = "nextpnr"; wr.vendor = "nextpnr";

2
ice40/cells.cc
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@ -69,7 +69,7 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6); new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6);
new_cell->params[ctx->id("PULLUP")] = Property::State::S0; new_cell->params[ctx->id("PULLUP")] = Property::State::S0;
new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0; new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
new_cell->params[ctx->id("IOSTANDARD")] = Property("SB_LVCMOS"); new_cell->params[ctx->id("IO_STANDARD")] = Property("SB_LVCMOS");
add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT); add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT);