Add read/mutate context stubs for ECP5

ecp5/arch.h

@@ -339,8 +339,10 @@ struct ArchArgs
 
 struct Arch : BaseCtx
 {
-    const ChipInfoPOD *chip_info;
+    // We let proxy methods access our state.
-
+    friend class ArchMutateMethods;
+    friend class ArchReadMethods;
+private:
     mutable std::unordered_map<IdString, BelId> bel_by_name;
     mutable std::unordered_map<IdString, WireId> wire_by_name;
     mutable std::unordered_map<IdString, PipId> pip_by_name;
@@ -350,6 +352,9 @@ struct Arch : BaseCtx
     std::unordered_map<PipId, IdString> pip_to_net;
     std::unordered_map<PipId, IdString> switches_locked;
 
+public:
+    const ChipInfoPOD *chip_info;
+
     ArchArgs args;
     Arch(ArchArgs args);
 
@@ -762,4 +767,100 @@ struct Arch : BaseCtx
     bool isBelLocationValid(BelId bel) const;
 };
 
+class ArchReadMethods : public BaseReadCtx
+{
+  private:
+    const Arch *parent_;
+    const ChipInfoPOD *chip_info;
+
+    const std::unordered_map<BelId, IdString> &bel_to_cell;
+    const std::unordered_map<WireId, IdString> &wire_to_net;
+    const std::unordered_map<PipId, IdString> &pip_to_net;
+    const std::unordered_map<PipId, IdString> &switches_locked;
+    std::unordered_map<IdString, BelId> &bel_by_name;
+    std::unordered_map<IdString, WireId> &wire_by_name;
+    std::unordered_map<IdString, PipId> &pip_by_name;
+
+  public:
+    ~ArchReadMethods() noexcept {}
+    ArchReadMethods(const Arch *parent)
+            : BaseReadCtx(parent), parent_(parent), chip_info(parent->chip_info), bel_to_cell(parent->bel_to_cell),
+              wire_to_net(parent->wire_to_net), pip_to_net(parent->pip_to_net),
+              switches_locked(parent->switches_locked), bel_by_name(parent->bel_by_name),
+              wire_by_name(parent->wire_by_name), pip_by_name(parent->pip_by_name)
+    {
+    }
+    ArchReadMethods(ArchReadMethods &&other) noexcept : ArchReadMethods(other.parent_) {}
+    ArchReadMethods(const ArchReadMethods &other) : ArchReadMethods(other.parent_) {}
+ 
+    /// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc)
+    // Whether or not a given cell can be placed at a given Bel
+    // This is not intended for Bel type checks, but finer-grained constraints
+    // such as conflicting set/reset signals, etc
+    bool isValidBelForCell(CellInfo *cell, BelId bel) const;
+    // Return true whether all Bels at a given location are valid
+    bool isBelLocationValid(BelId bel) const;
+    // Helper function for above
+    bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
+
+    bool checkWireAvail(WireId wire) const;
+    bool checkPipAvail(PipId pip) const;
+    bool checkBelAvail(BelId bel) const;
+
+    WireId getWireByName(IdString name) const;
+    WireId getWireBelPin(BelId bel, PortPin pin) const;
+    PipId getPipByName(IdString name) const;
+
+    IdString getConflictingWireNet(WireId wire) const;
+    IdString getConflictingPipNet(PipId pip) const;
+    IdString getConflictingBelCell(BelId bel) const;
+
+    IdString getBoundWireNet(WireId wire) const;
+    IdString getBoundPipNet(PipId pip) const;
+    IdString getBoundBelCell(BelId bel) const;
+
+    BelId getBelByName(IdString name) const;
+
+    std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
+};
+
+class ArchMutateMethods : public BaseMutateCtx
+{
+    friend class MutateContext;
+
+  private:
+    Arch *parent_;
+    const ChipInfoPOD *chip_info;
+
+    std::unordered_map<BelId, IdString> &bel_to_cell;
+    std::unordered_map<WireId, IdString> &wire_to_net;
+    std::unordered_map<PipId, IdString> &pip_to_net;
+    std::unordered_map<PipId, IdString> &switches_locked;
+    std::unordered_map<IdString, BelId> &bel_by_name;
+    std::unordered_map<IdString, WireId> &wire_by_name;
+    std::unordered_map<IdString, PipId> &pip_by_name;
+
+  public:
+    ~ArchMutateMethods() noexcept {}
+    ArchMutateMethods(Arch *parent)
+            : BaseMutateCtx(parent), parent_(parent), chip_info(parent->chip_info), bel_to_cell(parent->bel_to_cell),
+              wire_to_net(parent->wire_to_net), pip_to_net(parent->pip_to_net),
+              switches_locked(parent->switches_locked), bel_by_name(parent->bel_by_name),
+              wire_by_name(parent->wire_by_name), pip_by_name(parent->pip_by_name)
+    {
+    }
+    ArchMutateMethods(ArchMutateMethods &&other) noexcept : ArchMutateMethods(other.parent_) {}
+    ArchMutateMethods(const ArchMutateMethods &other) : ArchMutateMethods(other.parent_) {}
+
+    void unbindWire(WireId wire);
+    void unbindPip(PipId pip);
+    void unbindBel(BelId bel);
+    void bindWire(WireId wire, IdString net, PlaceStrength strength);
+    void bindPip(PipId pip, IdString net, PlaceStrength strength);
+    void bindBel(BelId bel, IdString cell, PlaceStrength strength);
+    // Returned pointer is valid as long as Proxy object exists.
+    CellInfo *getCell(IdString cell);
+};
+
+
 NEXTPNR_NAMESPACE_END

ice40/arch.h

@@ -345,7 +345,6 @@ class Arch : public BaseCtx
     friend class ArchReadMethods;
 
   private:
-    // All of the following...
     std::vector<IdString> bel_to_cell;
     std::vector<IdString> wire_to_net;
     std::vector<IdString> pip_to_net;
@@ -633,15 +632,12 @@ class ArchReadMethods : public BaseReadCtx
     ArchReadMethods(const ArchReadMethods &other) : ArchReadMethods(other.parent_) {}
 
     /// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc)
-
     // Whether or not a given cell can be placed at a given Bel
     // This is not intended for Bel type checks, but finer-grained constraints
     // such as conflicting set/reset signals, etc
     bool isValidBelForCell(CellInfo *cell, BelId bel) const;
-
     // Return true whether all Bels at a given location are valid
     bool isBelLocationValid(BelId bel) const;
-
     // Helper function for above
     bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;