Move BitstreamInfoPOD to ice40 chipdb blob

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ice40/bitstream.cc

@@ -155,7 +155,7 @@ void write_asc(const Design &design, std::ostream &out)
         const BelInfoPOD &beli = ci.bel_data[bel.index];
         int x = beli.x, y = beli.y, z = beli.z;
         if (cell.second->type == "ICESTORM_LC") {
-            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
+            const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
             unsigned lut_init = get_param_or_def(cell.second, "LUT_INIT");
             bool neg_clk = get_param_or_def(cell.second, "NEG_CLK");
             bool dff_enable = get_param_or_def(cell.second, "DFF_ENABLE");
@@ -181,7 +181,7 @@ void write_asc(const Design &design, std::ostream &out)
                            lc.at(i), i);
             set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
         } else if (cell.second->type == "SB_IO") {
-            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
+            const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
             unsigned pin_type = get_param_or_def(cell.second, "PIN_TYPE");
             bool neg_trigger = get_param_or_def(cell.second, "NEG_TRIGGER");
             bool pullup = get_param_or_def(cell.second, "PULLUP");
@@ -254,7 +254,7 @@ void write_asc(const Design &design, std::ostream &out)
     for (auto bel : chip.getBels()) {
         if (chip.bel_to_cell[bel.index] == IdString() &&
             chip.getBelType(bel) == TYPE_SB_IO) {
-            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
+            const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             auto ieren = get_ieren(bi, x, y, z);
@@ -273,7 +273,7 @@ void write_asc(const Design &design, std::ostream &out)
                    chip.getBelType(bel) == TYPE_ICESTORM_RAM) {
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y;
-            TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
+            const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_RAMB];
             if ((chip.args.type == ChipArgs::LP1K ||
                  chip.args.type == ChipArgs::HX1K)) {
                 set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true);
@@ -285,7 +285,7 @@ void write_asc(const Design &design, std::ostream &out)
     for (int y = 0; y < ci.height; y++) {
         for (int x = 0; x < ci.width; x++) {
             TileType tile = tile_at(chip, x, y);
-            TileInfoPOD &ti = bi.tiles_nonrouting[tile];
+            const TileInfoPOD &ti = bi.tiles_nonrouting[tile];
 
             // set all ColBufCtrl bits (FIXME)
             bool setColBufCtrl = true;

ice40/chip.h

@@ -201,10 +201,10 @@ struct IerenInfoPOD
 
 struct BitstreamInfoPOD
 {
-    int num_switches, num_ierens;
+    int32_t num_switches, num_ierens;
-    TileInfoPOD *tiles_nonrouting;
+    RelPtr<TileInfoPOD> tiles_nonrouting;
-    SwitchInfoPOD *switches;
+    RelPtr<SwitchInfoPOD> switches;
-    IerenInfoPOD *ierens;
+    RelPtr<IerenInfoPOD> ierens;
 } __attribute__((packed));
 
 struct ChipInfoPOD

ice40/chipdb.py

@@ -753,7 +753,7 @@ for switch in switches:
     si["bits"] = bitlist
     switchinfo.append(si)
 
-bba.l("switch_data_%s" % dev_name, "SwitchInfoPOD", export=True)
+bba.l("switch_data_%s" % dev_name, "SwitchInfoPOD")
 for info in switchinfo:
     bba.u32(len(info["bits"]), "num_bits")
     bba.u8(info["x"], "x")
@@ -766,14 +766,14 @@ for info in switchinfo:
             bba.u8(0, "row<%d> (unused)" % i)
             bba.u8(0, "col<%d> (unused)" % i)
 
-bba.l("tile_data_%s" % dev_name, "TileInfoPOD", export=True)
+bba.l("tile_data_%s" % dev_name, "TileInfoPOD")
 for info in tileinfo:
     bba.u8(info["cols"], "cols")
     bba.u8(info["rows"], "rows")
     bba.u16(info["num_entries"], "num_entries")
     bba.r(info["entries"], "entries")
 
-bba.l("ieren_data_%s" % dev_name, "IerenInfoPOD", export=True)
+bba.l("ieren_data_%s" % dev_name, "IerenInfoPOD")
 for ieren in ierens:
     bba.u8(ieren[0], "iox")
     bba.u8(ieren[1], "ioy")
@@ -782,16 +782,22 @@ for ieren in ierens:
     bba.u8(ieren[4], "iery")
     bba.u8(ieren[5], "ierz")
 
+if len(ierens) % 2 == 1:
+    bba.u16(0, "padding")
+
+bba.l("bits_info_%s" % dev_name, "BitstreamInfoPOD", export=True)
+bba.u32(len(switchinfo), "num_switches")
+bba.u32(len(ierens), "num_ierens")
+bba.r("tile_data_%s" % dev_name, "tiles_nonrouting")
+bba.r("switch_data_%s" % dev_name, "switches")
+bba.r("ieren_data_%s" % dev_name, "ierens")
+
 bba.finalize()
 if compact_output:
     bba.write_compact_c(sys.stdout)
 else:
     bba.write_verbose_c(sys.stdout)
 
-print("static BitstreamInfoPOD bits_info_%s = {" % dev_name)
-print("  %d, %d, tile_data_%s, switch_data_%s, ieren_data_%s" % (len(switchinfo), len(ierens), dev_name, dev_name, dev_name))
-print("};")
-
 print("static TileType tile_grid_%s[%d] = {" % (dev_name, len(tilegrid)))
 print("  " + ",\n  ".join(tilegrid))
 print("};")
@@ -806,7 +812,7 @@ print('NEXTPNR_NAMESPACE_BEGIN')
 print("ChipInfoPOD chip_info_%s = {" % dev_name)
 print("  %d, %d, %d, %d, %d, %d, %d," % (dev_width, dev_height, len(bel_name), num_wires, len(pipinfo), len(switchinfo), len(packageinfo)))
 print("  bel_data, wire_data_%s, pip_data_%s," % (dev_name, dev_name))
-print("  tile_grid_%s, &bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
+print("  tile_grid_%s, bits_info_%s, package_info_%s" % (dev_name, dev_name, dev_name))
 print("};")
 
 print('NEXTPNR_NAMESPACE_END')