caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clangformat

Browse Source
This commit is contained in:
Eddie Hung 2018-08-06 17:35:23 -07:00
parent 483f863106
commit f44a5fb904
4 changed files with 57 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
common/timing.cc
View File

@ -20,11 +20,11 @@
#include "timing.h" #include "timing.h"
#include <algorithm> #include <algorithm>
#include <boost/range/adaptor/reversed.hpp>
#include <unordered_map> #include <unordered_map>
#include <utility> #include <utility>
#include "log.h" #include "log.h"
#include "util.h" #include "util.h"
#include <boost/range/adaptor/reversed.hpp>
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
@ -40,7 +40,8 @@ struct Timing
PortRefVector *crit_path; PortRefVector *crit_path;
DelayFrequency *slack_histogram; DelayFrequency *slack_histogram;
struct TimingData { struct TimingData
{
TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {} TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {} TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
delay_t max_arrival; delay_t max_arrival;
@ -61,20 +62,22 @@ struct Timing
// First, compute the topographical order of nets to walk through // First, compute the topographical order of nets to walk through
// the circuit, assuming it is a _acyclic_ graph // the circuit, assuming it is a _acyclic_ graph
// TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops // TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial
std::vector<NetInfo*> topographical_order; // loops
std::unordered_map<const NetInfo*, TimingData> net_data; std::vector<NetInfo *> topographical_order;
std::unordered_map<const NetInfo *, TimingData> net_data;
// In lieu of deleting edges from the graph, simply count // In lieu of deleting edges from the graph, simply count
// the number of fanins to each output port // the number of fanins to each output port
std::unordered_map<const PortInfo*, unsigned> port_fanin; std::unordered_map<const PortInfo *, unsigned> port_fanin;
std::vector<IdString> input_ports; std::vector<IdString> input_ports;
std::vector<const PortInfo*> output_ports; std::vector<const PortInfo *> output_ports;
for (auto &cell : ctx->cells) { for (auto &cell : ctx->cells) {
input_ports.clear(); input_ports.clear();
output_ports.clear(); output_ports.clear();
for (auto& port : cell.second->ports) { for (auto &port : cell.second->ports) {
if (!port.second.net) continue; if (!port.second.net)
continue;
if (port.second.type == PORT_OUT) if (port.second.type == PORT_OUT)
output_ports.push_back(&port.second); output_ports.push_back(&port.second);
else else
@ -90,11 +93,10 @@ struct Timing
DelayInfo clkToQ; DelayInfo clkToQ;
ctx->getCellDelay(cell.second.get(), clock_domain, o->name, clkToQ); ctx->getCellDelay(cell.second.get(), clock_domain, o->name, clkToQ);
topographical_order.emplace_back(o->net); topographical_order.emplace_back(o->net);
net_data.emplace(o->net, TimingData{ clkToQ.maxDelay() }); net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
} } else {
else {
// Also add I/O cells too // Also add I/O cells too
// TODO(eddieh): More generic way of detecting PLLs // TODO(eddieh): More generic way of detecting PLLs
if (is_io || cell.second->type == ctx->id("ICESTORM_PLL")) { if (is_io || cell.second->type == ctx->id("ICESTORM_PLL")) {
topographical_order.emplace_back(o->net); topographical_order.emplace_back(o->net);
net_data.emplace(o->net, TimingData{}); net_data.emplace(o->net, TimingData{});
@ -124,9 +126,10 @@ struct Timing
net_data.emplace(it->second.get(), TimingData{}); net_data.emplace(it->second.get(), TimingData{});
} }
std::deque<NetInfo*> queue(topographical_order.begin(), topographical_order.end()); std::deque<NetInfo *> queue(topographical_order.begin(), topographical_order.end());
// Now walk the design, from the start points identified previously, building // Now walk the design, from the start points identified previously,
// building
// up a topographical order // up a topographical order
while (!queue.empty()) { while (!queue.empty()) {
const auto net = queue.front(); const auto net = queue.front();
@ -135,7 +138,7 @@ struct Timing
DelayInfo clkToQ; DelayInfo clkToQ;
for (auto &usr : net->users) { for (auto &usr : net->users) {
auto clock_domain = ctx->getPortClock(usr.cell, usr.port); auto clock_domain = ctx->getPortClock(usr.cell, usr.port);
for (auto& port : usr.cell->ports) { for (auto &port : usr.cell->ports) {
if (port.second.type == PORT_OUT && port.second.net) { if (port.second.type == PORT_OUT && port.second.net) {
// Skip if this is a clocked output (but allow non-clocked ones) // Skip if this is a clocked output (but allow non-clocked ones)
if (clock_domain != IdString() && ctx->getCellDelay(usr.cell, clock_domain, port.first, clkToQ)) if (clock_domain != IdString() && ctx->getCellDelay(usr.cell, clock_domain, port.first, clkToQ))
@ -182,12 +185,13 @@ struct Timing
// Look up delay through this path // Look up delay through this path
bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay); bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
if (is_path) { if (is_path) {
auto& data = net_data[port.second.net]; auto &data = net_data[port.second.net];
auto& arrival = data.max_arrival; auto &arrival = data.max_arrival;
arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay()); arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
if (!budget_override) { // Do not increment path length if budget overriden if (!budget_override) { // Do not increment path length if
// since it doesn't require a share of the slack // budget overriden
auto& path_length = data.max_path_length; // since it doesn't require a share of the slack
auto &path_length = data.max_path_length;
path_length = std::max(path_length, net_length_plus_one); path_length = std::max(path_length, net_length_plus_one);
} }
} }
@ -197,14 +201,14 @@ struct Timing
} }
} }
const NetInfo* crit_net = nullptr; const NetInfo *crit_net = nullptr;
// Now go backwards topographically to determine the minimum path slack, // Now go backwards topographically to determine the minimum path slack,
// and to distribute all path slack evenly between all nets on the path // and to distribute all path slack evenly between all nets on the path
for (auto net : boost::adaptors::reverse(topographical_order)) { for (auto net : boost::adaptors::reverse(topographical_order)) {
auto &nd = net_data.at(net); auto &nd = net_data.at(net);
const delay_t net_length_plus_one = nd.max_path_length + 1; const delay_t net_length_plus_one = nd.max_path_length + 1;
auto& net_min_remaining_budget = nd.min_remaining_budget; auto &net_min_remaining_budget = nd.min_remaining_budget;
for (auto &usr : net->users) { for (auto &usr : net->users) {
auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t(); auto net_delay = net_delays ? ctx->getNetinfoRouteDelay(net, usr) : delay_t();
auto budget_override = ctx->getBudgetOverride(net, usr, net_delay); auto budget_override = ctx->getBudgetOverride(net, usr, net_delay);
@ -230,7 +234,7 @@ struct Timing
} }
} else { } else {
// Iterate over all output ports on the same cell as the sink // Iterate over all output ports on the same cell as the sink
for (const auto& port : usr.cell->ports) { for (const auto &port : usr.cell->ports) {
if (port.second.type == PORT_OUT && port.second.net) { if (port.second.type == PORT_OUT && port.second.net) {
DelayInfo comb_delay; DelayInfo comb_delay;
bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay); bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
@ -239,7 +243,8 @@ struct Timing
auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one; auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
if (update) if (update)
usr.budget = std::min(usr.budget, net_delay + budget_share); usr.budget = std::min(usr.budget, net_delay + budget_share);
net_min_remaining_budget = std::min(net_min_remaining_budget, path_budget - budget_share); net_min_remaining_budget =
std::min(net_min_remaining_budget, path_budget - budget_share);
} }
} }
} }
@ -250,14 +255,15 @@ struct Timing
if (crit_path) { if (crit_path) {
// Walk backwards from the most critical net // Walk backwards from the most critical net
while (crit_net) { while (crit_net) {
const PortInfo* crit_ipin = nullptr; const PortInfo *crit_ipin = nullptr;
delay_t max_arrival = std::numeric_limits<delay_t>::min(); delay_t max_arrival = std::numeric_limits<delay_t>::min();
// Look at all input ports on its driving cell // Look at all input ports on its driving cell
for (const auto& port : crit_net->driver.cell->ports) { for (const auto &port : crit_net->driver.cell->ports) {
if (port.second.type == PORT_IN && port.second.net) { if (port.second.type == PORT_IN && port.second.net) {
DelayInfo comb_delay; DelayInfo comb_delay;
bool is_path = ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay); bool is_path =
ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
if (is_path) { if (is_path) {
// If input port is influenced by a clock, skip // If input port is influenced by a clock, skip
if (ctx->getPortClock(crit_net->driver.cell, port.first) != IdString()) if (ctx->getPortClock(crit_net->driver.cell, port.first) != IdString())
@ -273,7 +279,8 @@ struct Timing
} }
} }
if (!crit_ipin) break; if (!crit_ipin)
break;
for (auto &usr : crit_ipin->net->users) { for (auto &usr : crit_ipin->net->users) {
if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) { if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {

7
ecp5/arch.cc
View File

@ -375,7 +375,6 @@ BelId Arch::getPioByFunctionName(const std::string &name) const
} }
std::vector<PortPin> Arch::getBelPins(BelId bel) const std::vector<PortPin> Arch::getBelPins(BelId bel) const
{ {
std::vector<PortPin> ret; std::vector<PortPin> ret;
NPNR_ASSERT(bel != BelId()); NPNR_ASSERT(bel != BelId());
@ -500,11 +499,7 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return
bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; } bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
bool Arch::isIOCell(const CellInfo *cell) const bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id("TRELLIS_IO"); }
{
return cell->type == id("TRELLIS_IO");
}
std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col) std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
{ {

22
ice40/arch.cc
View File

@ -291,7 +291,8 @@ BelId Arch::getBelByLocation(Loc loc) const
BelRange Arch::getBelsByTile(int x, int y) const BelRange Arch::getBelsByTile(int x, int y) const
{ {
// In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates
// are used
BelRange br; BelRange br;
br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index; br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
@ -645,23 +646,27 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
auto sink_loc = getBelLocation(sink.cell->bel); auto sink_loc = getBelLocation(sink.cell->bel);
if (driver_loc.y == sink_loc.y) if (driver_loc.y == sink_loc.y)
budget = 0; budget = 0;
else switch (args.type) { else
switch (args.type) {
#ifndef ICE40_HX1K_ONLY #ifndef ICE40_HX1K_ONLY
case ArchArgs::HX8K: case ArchArgs::HX8K:
#endif #endif
case ArchArgs::HX1K: case ArchArgs::HX1K:
budget = 190; break; budget = 190;
break;
#ifndef ICE40_HX1K_ONLY #ifndef ICE40_HX1K_ONLY
case ArchArgs::LP384: case ArchArgs::LP384:
case ArchArgs::LP1K: case ArchArgs::LP1K:
case ArchArgs::LP8K: case ArchArgs::LP8K:
budget = 290; break; budget = 290;
break;
case ArchArgs::UP5K: case ArchArgs::UP5K:
budget = 560; break; budget = 560;
break;
#endif #endif
default: default:
log_error("Unsupported iCE40 chip type.\n"); log_error("Unsupported iCE40 chip type.\n");
} }
return true; return true;
} }
return false; return false;
@ -913,10 +918,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const
return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out; return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
} }
bool Arch::isIOCell(const CellInfo *cell) const bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id_sb_io; }
{
return cell->type == id_sb_io;
}
// Assign arch arg info // Assign arch arg info
void Arch::assignArchInfo() void Arch::assignArchInfo()

14
ice40/arch.h
View File

@ -400,10 +400,10 @@ struct Arch : BaseCtx
mutable std::unordered_map<Loc, int> bel_by_loc; mutable std::unordered_map<Loc, int> bel_by_loc;
std::vector<bool> bel_carry; std::vector<bool> bel_carry;
std::vector<CellInfo*> bel_to_cell; std::vector<CellInfo *> bel_to_cell;
std::vector<NetInfo*> wire_to_net; std::vector<NetInfo *> wire_to_net;
std::vector<NetInfo*> pip_to_net; std::vector<NetInfo *> pip_to_net;
std::vector<NetInfo*> switches_locked; std::vector<NetInfo *> switches_locked;
ArchArgs args; ArchArgs args;
Arch(ArchArgs args); Arch(ArchArgs args);
@ -799,7 +799,8 @@ struct Arch : BaseCtx
// ------------------------------------------------- // -------------------------------------------------
// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc) // Perform placement validity checks, returning false on failure (all
// implemented in arch_place.cc)
// Whether or not a given cell can be placed at a given Bel // Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints // This is not intended for Bel type checks, but finer-grained constraints
@ -813,7 +814,8 @@ struct Arch : BaseCtx
bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const; bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
// ------------------------------------------------- // -------------------------------------------------
// Assign architecure-specific arguments to nets and cells, which must be called between packing or further // Assign architecure-specific arguments to nets and cells, which must be
// called between packing or further
// netlist modifications, and validity checks // netlist modifications, and validity checks
void assignArchInfo(); void assignArchInfo();
void assignCellInfo(CellInfo *cell); void assignCellInfo(CellInfo *cell);