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This commit is contained in:
Eddie Hung 2018-08-06 17:35:23 -07:00
parent 483f863106
commit f44a5fb904
4 changed files with 57 additions and 51 deletions
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29
common/timing.cc
View File

@ -20,11 +20,11 @@
#include "timing.h"
#include <algorithm>
#include <boost/range/adaptor/reversed.hpp>
#include <unordered_map>
#include <utility>
#include "log.h"
#include "util.h"
#include <boost/range/adaptor/reversed.hpp>
NEXTPNR_NAMESPACE_BEGIN
@ -40,7 +40,8 @@ struct Timing
PortRefVector *crit_path;
DelayFrequency *slack_histogram;
struct TimingData {
struct TimingData
{
TimingData() : max_arrival(), max_path_length(), min_remaining_budget() {}
TimingData(delay_t max_arrival) : max_arrival(max_arrival), max_path_length(), min_remaining_budget() {}
delay_t max_arrival;
@ -61,7 +62,8 @@ struct Timing
// First, compute the topographical order of nets to walk through
// the circuit, assuming it is a _acyclic_ graph
// TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
// TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial
// loops
std::vector<NetInfo *> topographical_order;
std::unordered_map<const NetInfo *, TimingData> net_data;
// In lieu of deleting edges from the graph, simply count
@ -74,7 +76,8 @@ struct Timing
input_ports.clear();
output_ports.clear();
for (auto &port : cell.second->ports) {
if (!port.second.net) continue;
if (!port.second.net)
continue;
if (port.second.type == PORT_OUT)
output_ports.push_back(&port.second);
else
@ -91,8 +94,7 @@ struct Timing
ctx->getCellDelay(cell.second.get(), clock_domain, o->name, clkToQ);
topographical_order.emplace_back(o->net);
net_data.emplace(o->net, TimingData{clkToQ.maxDelay()});
}
else {
} else {
// Also add I/O cells too
// TODO(eddieh): More generic way of detecting PLLs
if (is_io || cell.second->type == ctx->id("ICESTORM_PLL")) {
@ -126,7 +128,8 @@ struct Timing
std::deque<NetInfo *> queue(topographical_order.begin(), topographical_order.end());
// Now walk the design, from the start points identified previously, building
// Now walk the design, from the start points identified previously,
// building
// up a topographical order
while (!queue.empty()) {
const auto net = queue.front();
@ -185,7 +188,8 @@ struct Timing
auto &data = net_data[port.second.net];
auto &arrival = data.max_arrival;
arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
if (!budget_override) { // Do not increment path length if budget overriden
if (!budget_override) { // Do not increment path length if
// budget overriden
// since it doesn't require a share of the slack
auto &path_length = data.max_path_length;
path_length = std::max(path_length, net_length_plus_one);
@ -239,7 +243,8 @@ struct Timing
auto budget_share = budget_override ? 0 : path_budget / net_length_plus_one;
if (update)
usr.budget = std::min(usr.budget, net_delay + budget_share);
net_min_remaining_budget = std::min(net_min_remaining_budget, path_budget - budget_share);
net_min_remaining_budget =
std::min(net_min_remaining_budget, path_budget - budget_share);
}
}
}
@ -257,7 +262,8 @@ struct Timing
for (const auto &port : crit_net->driver.cell->ports) {
if (port.second.type == PORT_IN && port.second.net) {
DelayInfo comb_delay;
bool is_path = ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
bool is_path =
ctx->getCellDelay(crit_net->driver.cell, port.first, crit_net->driver.port, comb_delay);
if (is_path) {
// If input port is influenced by a clock, skip
if (ctx->getPortClock(crit_net->driver.cell, port.first) != IdString())
@ -273,7 +279,8 @@ struct Timing
}
}
if (!crit_ipin) break;
if (!crit_ipin)
break;
for (auto &usr : crit_ipin->net->users) {
if (usr.cell->name == crit_net->driver.cell->name && usr.port == crit_ipin->name) {

7
ecp5/arch.cc
View File

@ -375,7 +375,6 @@ BelId Arch::getPioByFunctionName(const std::string &name) const
}
std::vector<PortPin> Arch::getBelPins(BelId bel) const
{
std::vector<PortPin> ret;
NPNR_ASSERT(bel != BelId());
@ -500,11 +499,7 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return
bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
bool Arch::isIOCell(const CellInfo *cell) const
{
return cell->type == id("TRELLIS_IO");
}
bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id("TRELLIS_IO"); }
std::vector<std::pair<std::string, std::string>> Arch::getTilesAtLocation(int row, int col)
{

20
ice40/arch.cc
View File

@ -291,7 +291,8 @@ BelId Arch::getBelByLocation(Loc loc) const
BelRange Arch::getBelsByTile(int x, int y) const
{
// In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used
// In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates
// are used
BelRange br;
br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
@ -645,19 +646,23 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
auto sink_loc = getBelLocation(sink.cell->bel);
if (driver_loc.y == sink_loc.y)
budget = 0;
else switch (args.type) {
else
switch (args.type) {
#ifndef ICE40_HX1K_ONLY
case ArchArgs::HX8K:
#endif
case ArchArgs::HX1K:
budget = 190; break;
budget = 190;
break;
#ifndef ICE40_HX1K_ONLY
case ArchArgs::LP384:
case ArchArgs::LP1K:
case ArchArgs::LP8K:
budget = 290; break;
budget = 290;
break;
case ArchArgs::UP5K:
budget = 560; break;
budget = 560;
break;
#endif
default:
log_error("Unsupported iCE40 chip type.\n");
@ -913,10 +918,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const
return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
}
bool Arch::isIOCell(const CellInfo *cell) const
{
return cell->type == id_sb_io;
}
bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id_sb_io; }
// Assign arch arg info
void Arch::assignArchInfo()

6
ice40/arch.h
View File

@ -799,7 +799,8 @@ struct Arch : BaseCtx
// -------------------------------------------------
// Perform placement validity checks, returning false on failure (all implemented in arch_place.cc)
// Perform placement validity checks, returning false on failure (all
// implemented in arch_place.cc)
// Whether or not a given cell can be placed at a given Bel
// This is not intended for Bel type checks, but finer-grained constraints
@ -813,7 +814,8 @@ struct Arch : BaseCtx
bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
// -------------------------------------------------
// Assign architecure-specific arguments to nets and cells, which must be called between packing or further
// Assign architecure-specific arguments to nets and cells, which must be
// called between packing or further
// netlist modifications, and validity checks
void assignArchInfo();
void assignCellInfo(CellInfo *cell);