himbaechel/gowin: add timing information
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Lofty
parent
f17caa2379
commit
f4ea2322e3
@ -654,7 +654,7 @@ class TimingPool(BBAStruct):
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def set_bel_pin_class(self, grade: str, name: str, delay: TimingValue,
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in_cap: Optional[TimingValue]=None, out_res: Optional[TimingValue]=None):
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# bel pin classes are shared with pip classes, but this alias adds a bit of extra clarity
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set_pip_class(self, grade, name, delay, in_cap, out_res, is_buffered=True)
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self.set_pip_class(grade, name, delay, in_cap, out_res, is_buffered=True)
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def set_node_class(self, grade: str, name: str, delay: TimingValue,
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res: Optional[TimingValue]=None, cap: Optional[TimingValue]=None):
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@ -160,10 +160,12 @@ void GowinImpl::init(Context *ctx)
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if (std::regex_match(pn, match, speedre)) {
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package_idx = ctx->id(match[1]);
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spd = ctx->id(match[2]);
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ctx->set_speed_grade(match[2]);
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} else {
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if (pn.length() > 2 && pn.compare(pn.length() - 2, 2, "ES")) {
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package_idx = ctx->id(pn.substr(pn.length() - 2));
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spd = ctx->id("ES");
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ctx->set_speed_grade("ES");
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}
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}
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@ -185,6 +185,11 @@ class TypeDesc:
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self.sfx = sfx
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created_tiletypes = {}
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# get timing class by wire name
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def get_tm_class(db: chipdb, wire: str):
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assert wire in db.wire_delay, f"Unknown timing class for {wire}"
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return db.wire_delay[wire]
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# u-turn at the rim
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uturnlut = {'N': 'S', 'S': 'N', 'E': 'W', 'W': 'E'}
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def uturn(db: chipdb, x: int, y: int, wire: str):
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@ -295,9 +300,11 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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if not tt.has_wire(dst):
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tt.create_wire(dst, get_wire_type(dst))
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for src in srcs.keys():
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if src not in db.wire_delay:
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continue
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if not tt.has_wire(src):
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tt.create_wire(src, get_wire_type(src))
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tt.create_pip(src, dst)
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tt.create_pip(src, dst, get_tm_class(db, src))
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# clock wires
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for dst, srcs in db.grid[y][x].pure_clock_pips.items():
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@ -306,7 +313,7 @@ def create_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "GLOBAL_CLK")
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tt.create_pip(src, dst)
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tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
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def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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if (y, x) not in db.hclk_pips:
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@ -318,7 +325,7 @@ def create_hclk_switch_matrix(tt: TileType, db: chipdb, x: int, y: int):
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for src in srcs.keys():
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if not tt.has_wire(src):
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tt.create_wire(src, "HCLK")
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tt.create_pip(src, dst)
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tt.create_pip(src, dst, get_tm_class(db, "X01")) # XXX
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def create_extra_funcs(tt: TileType, db: chipdb, x: int, y: int):
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if (y, x) not in db.extra_func:
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@ -548,7 +555,7 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
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# setup LUT wires
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for i in range(8):
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for inp_name in lut_inputs:
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tt.create_wire(f"{inp_name}{i}", "LUT_INPUT")
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tt.create_wire(f"{inp_name}{i}", "LUT_IN")
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tt.create_wire(f"F{i}", "LUT_OUT")
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# experimental. the wire is false - it is assumed that DFF is always
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# connected to the LUT's output F{i}, but we can place primitives
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@ -581,9 +588,9 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
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if i < 6:
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# FF data can come from LUT output, but we pretend that we can use
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# any LUT input
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tt.create_pip(f"F{i}", f"XD{i}")
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tt.create_pip(f"F{i}", f"XD{i}", get_tm_class(db, f"F{i}"))
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for inp_name in lut_inputs:
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tt.create_pip(f"{inp_name}{i}", f"XD{i}")
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tt.create_pip(f"{inp_name}{i}", f"XD{i}", get_tm_class(db, f"{inp_name}{i}"))
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# FF
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ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
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tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
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@ -1006,6 +1013,134 @@ def create_extra_data(chip: Chip, db: chipdb, chip_flags: int):
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for diff_type in db.diff_io_types:
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chip.extra_data.add_diff_io_type(diff_type)
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def create_timing_info(chip: Chip, db: chipdb.Device):
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def group_to_timingvalue(group):
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# if himbaechel ever recognises unateness, this should match that order.
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ff = int(group[0] * 1000)
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fr = int(group[1] * 1000)
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rr = int(group[2] * 1000)
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rf = int(group[3] * 1000)
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return TimingValue(min(ff, fr, rf, rr), max(ff, fr, rf, rr))
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speed_grades = []
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for speed, _ in db.timing.items():
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speed_grades.append(speed)
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tmg = chip.set_speed_grades(speed_grades)
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print("device {}:".format(chip.name))
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for speed, groups in db.timing.items():
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for group, arc in groups.items():
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if group == "lut":
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lut = tmg.add_cell_variant(speed, "LUT4")
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lut.add_comb_arc("I0", "F", group_to_timingvalue(arc["a_f"]))
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lut.add_comb_arc("I1", "F", group_to_timingvalue(arc["b_f"]))
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lut.add_comb_arc("I2", "F", group_to_timingvalue(arc["c_f"]))
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lut.add_comb_arc("I3", "F", group_to_timingvalue(arc["d_f"]))
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mux5 = tmg.add_cell_variant(speed, "MUX2_LUT5")
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mux5.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
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mux5.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
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mux5.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
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mux6 = tmg.add_cell_variant(speed, "MUX2_LUT6")
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mux6.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
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mux6.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
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mux6.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
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mux7 = tmg.add_cell_variant(speed, "MUX2_LUT7")
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mux7.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
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mux7.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
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mux7.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
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mux8 = tmg.add_cell_variant(speed, "MUX2_LUT8")
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mux8.add_comb_arc("I0", "O", group_to_timingvalue(arc["m0_ofx0"]))
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mux8.add_comb_arc("I1", "O", group_to_timingvalue(arc["m1_ofx1"]))
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mux8.add_comb_arc("S0", "O", group_to_timingvalue(arc["fx_ofx1"]))
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elif group == "alu":
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alu = tmg.add_cell_variant(speed, "ALU")
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alu.add_comb_arc("I0", "SUM", group_to_timingvalue(arc["a_f"]))
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alu.add_comb_arc("I1", "SUM", group_to_timingvalue(arc["b_f"]))
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alu.add_comb_arc("I3", "SUM", group_to_timingvalue(arc["d_f"]))
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alu.add_comb_arc("CIN", "SUM", group_to_timingvalue(arc["fci_f0"]))
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alu.add_comb_arc("I0", "COUT", group_to_timingvalue(arc["a0_fco"]))
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alu.add_comb_arc("I1", "COUT", group_to_timingvalue(arc["b0_fco"]))
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alu.add_comb_arc("I3", "COUT", group_to_timingvalue(arc["d0_fco"]))
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alu.add_comb_arc("CIN", "COUT", group_to_timingvalue(arc["fci_fco"]))
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elif group == "sram":
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sram = tmg.add_cell_variant(speed, "RAM16SDP4")
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for do in range(4):
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for rad in range(4):
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sram.add_comb_arc(f"RAD[{rad}]", f"DO[{do}]", group_to_timingvalue(arc[f"rad{rad}_do"]))
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sram.add_clock_out("CLK", f"DO[{do}]", ClockEdge.RISING, group_to_timingvalue(arc["clk_do"]))
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for di in range(4):
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sram.add_setup_hold("CLK", f"DI[{di}", ClockEdge.RISING, group_to_timingvalue(arc["clk_di_set"]), group_to_timingvalue(arc["clk_di_hold"]))
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sram.add_setup_hold("CLK", "WRE", ClockEdge.RISING, group_to_timingvalue(arc["clk_wre_set"]), group_to_timingvalue(arc["clk_wre_hold"]))
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for wad in range(4):
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sram.add_setup_hold("CLK", f"WAD[{wad}]", ClockEdge.RISING, group_to_timingvalue(arc[f"clk_wad{wad}_set"]), group_to_timingvalue(arc[f"clk_wad{wad}_hold"]))
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elif group == "dff":
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for reset_type in ('', 'P', 'C', 'S', 'R'):
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for clock_enable in ('', 'E'):
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cell_name = "DFF{}{}".format(reset_type, clock_enable)
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dff = tmg.add_cell_variant(speed, cell_name)
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dff.add_setup_hold("CLK", "D", ClockEdge.RISING, group_to_timingvalue(arc["di_clksetpos"]), group_to_timingvalue(arc["di_clkholdpos"]))
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dff.add_setup_hold("CLK", "CE", ClockEdge.RISING, group_to_timingvalue(arc["ce_clksetpos"]), group_to_timingvalue(arc["ce_clkholdpos"]))
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dff.add_clock_out("CLK", "Q", ClockEdge.RISING, group_to_timingvalue(arc["clk_qpos"]))
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if reset_type in ('S', 'R'):
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port = "RESET" if reset_type == 'R' else "SET"
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dff.add_setup_hold("CLK", port, ClockEdge.RISING, group_to_timingvalue(arc["lsr_clksetpos_syn"]), group_to_timingvalue(arc["lsr_clkholdpos_syn"]))
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elif reset_type in ('P', 'C'):
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port = "CLEAR" if reset_type == 'C' else "PRESET"
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dff.add_setup_hold("CLK", port, ClockEdge.RISING, group_to_timingvalue(arc["lsr_clksetpos_asyn"]), group_to_timingvalue(arc["lsr_clkholdpos_asyn"]))
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dff.add_comb_arc(port, "Q", group_to_timingvalue(arc["lsr_q"]))
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cell_name = "DFFN{}{}".format(reset_type, clock_enable)
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dff = tmg.add_cell_variant(speed, cell_name)
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dff.add_setup_hold("CLK", "D", ClockEdge.FALLING, group_to_timingvalue(arc["di_clksetneg"]), group_to_timingvalue(arc["di_clkholdneg"]))
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dff.add_setup_hold("CLK", "CE", ClockEdge.FALLING, group_to_timingvalue(arc["ce_clksteneg"]), group_to_timingvalue(arc["ce_clkholdneg"])) # the DBs have a typo...
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dff.add_clock_out("CLK", "Q", ClockEdge.FALLING, group_to_timingvalue(arc["clk_qneg"]))
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if reset_type in ('S', 'R'):
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port = "RESET" if reset_type == 'R' else "SET"
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dff.add_setup_hold("CLK", port, ClockEdge.FALLING, group_to_timingvalue(arc["lsr_clksetneg_syn"]), group_to_timingvalue(arc["lsr_clkholdneg_syn"]))
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elif reset_type in ('P', 'C'):
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port = "CLEAR" if reset_type == 'C' else "PRESET"
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dff.add_setup_hold("CLK", port, ClockEdge.FALLING, group_to_timingvalue(arc["lsr_clksetneg_asyn"]), group_to_timingvalue(arc["lsr_clkholdneg_asyn"]))
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dff.add_comb_arc(port, "Q", group_to_timingvalue(arc["lsr_q"]))
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elif group == "bram":
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pass # TODO
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elif group == "fanout":
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pass # handled in "wire"
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elif group == "glbsrc":
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pass # TODO
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elif group == "hclk":
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pass # TODO
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elif group == "iodelay":
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pass # TODO
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elif group == "wire":
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# wires with delay and fanout delay
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for name in ["X0", "X2", "X8"]:
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tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]), group_to_timingvalue(groups["fanout"][f"{name}Fan"]), TimingValue(round(1e6 / groups["fanout"][f"{name}FanNum"])))
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# wires with delay but no fanout delay
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for name in ["X0CTL", "X0CLK", "FX1"]:
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tmg.set_pip_class(speed, name, group_to_timingvalue(arc[name]))
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# wires with presently-unknown delay
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for name in ["LUT_IN", "DI", "SEL", "CIN", "COUT", "VCC", "VSS", "LW_TAP", "LW_TAP_0", "LW_BRANCH", "LW_SPAN", "GCLK_TAP", "GCLK_BRANCH"]:
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tmg.set_pip_class(speed, name, TimingValue())
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# wires with fanout-only delay; used on cell output pips
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for name, mapping in [("LUT_OUT", "FFan"), ("FF_OUT", "QFan"), ("OF", "OFFan")]:
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tmg.set_pip_class(speed, name, TimingValue(), group_to_timingvalue(groups["fanout"][mapping]), TimingValue(round(1e6 / groups["fanout"][f"{mapping}Num"])))
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print("speed {}:".format(speed))
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for group, arc in groups.items():
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print(" group {}:".format(group))
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for name, items in arc.items():
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print(" name {}:".format(str(name)))
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try:
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items[0]
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for item in items:
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print(" item {}".format(item))
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except TypeError:
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print(" item {}".format(items))
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continue
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def main():
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parser = argparse.ArgumentParser(description='Make Gowin BBA')
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parser.add_argument('-d', '--device', required=True)
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@ -1081,6 +1216,7 @@ def main():
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# Create nodes between tiles
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create_nodes(ch, db)
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create_extra_data(ch, db, chip_flags)
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create_timing_info(ch, db)
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ch.write_bba(args.output)
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if __name__ == '__main__':
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main()
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