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cleanup and constids

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This commit is contained in:
Miodrag Milanovic 2024-11-27 16:59:17 +01:00
parent 77a97f93bd
commit f62c33f099
6 changed files with 233 additions and 232 deletions
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250
himbaechel/uarch/ng-ultra/bitstream.cc
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@ -125,7 +125,7 @@ struct BitstreamJsonBackend
bool first_net = true;
for (auto &net : ctx->nets) {
NetInfo *ni = net.second.get();
if (ni->wires.size()==0) continue;
if (ni->wires.empty()) continue;
out << (first_net ? "" : ",\n"); first_net = false;
out << stringf("\t\t%s: [\n", get_string(cleanup_name(ni->name.c_str(ctx))).c_str());
std::set<std::string> nets;
@ -270,26 +270,26 @@ struct BitstreamJsonBackend
}
void write_iop(CellInfo *cell) {
open_instance(cell, str_or_default(cell->params, ctx->id("iobname"), ""));
add_config("location", str_or_default(cell->params, ctx->id("location"), ""));
add_config("differential", str_or_n_value_lower(cell->params, ctx->id("differential"), "false"));
add_config("slewRate", str_or_default(cell->params, ctx->id("slewRate"), "Medium"));
add_config("turbo", str_or_n_value_lower(cell->params, ctx->id("turbo"), "false"));
add_config("weakTermination", str_or_n_value(cell->params, ctx->id("weakTermination"), "PullUp"));
add_config("inputDelayLine", str_or_default(cell->params, ctx->id("inputDelayLine"), "0"));
add_config("outputDelayLine", str_or_default(cell->params, ctx->id("outputDelayLine"), "0"));
add_config("inputSignalSlope", str_or_default(cell->params, ctx->id("inputSignalSlope"), "0"));
add_config("outputCapacity", str_or_default(cell->params, ctx->id("outputCapacity"), "0"));
add_config("standard", str_or_default(cell->params, ctx->id("standard"), "LVCMOS"));
add_config("drive", str_or_default(cell->params, ctx->id("drive"), "2mA"));
add_config("inputDelayOn", str_or_n_value_lower(cell->params, ctx->id("inputDelayOn"), "false"));
add_config("outputDelayOn", str_or_n_value_lower(cell->params, ctx->id("outputDelayOn"), "false"));
add_config("dynDrive", str_or_n_value_lower(cell->params, ctx->id("dynDrive"), "false"));
add_config("dynInput", str_or_n_value_lower(cell->params, ctx->id("dynInput"), "false"));
add_config("dynTerm", str_or_n_value_lower(cell->params, ctx->id("dynTerm"), "false"));
open_instance(cell, str_or_default(cell->params, id_iobname, ""));
add_config("location", str_or_default(cell->params, id_location, ""));
add_config("differential", str_or_n_value_lower(cell->params, id_differential, "false"));
add_config("slewRate", str_or_default(cell->params, id_slewRate, "Medium"));
add_config("turbo", str_or_n_value_lower(cell->params, id_turbo, "false"));
add_config("weakTermination", str_or_n_value(cell->params, id_weakTermination, "PullUp"));
add_config("inputDelayLine", str_or_default(cell->params, id_inputDelayLine, "0"));
add_config("outputDelayLine", str_or_default(cell->params, id_outputDelayLine, "0"));
add_config("inputSignalSlope", str_or_default(cell->params, id_inputSignalSlope, "0"));
add_config("outputCapacity", str_or_default(cell->params, id_outputCapacity, "0"));
add_config("standard", str_or_default(cell->params, id_standard, "LVCMOS"));
add_config("drive", str_or_default(cell->params, id_drive, "2mA"));
add_config("inputDelayOn", str_or_n_value_lower(cell->params, id_inputDelayOn, "false"));
add_config("outputDelayOn", str_or_n_value_lower(cell->params, id_outputDelayOn, "false"));
add_config("dynDrive", str_or_n_value_lower(cell->params, id_dynDrive, "false"));
add_config("dynInput", str_or_n_value_lower(cell->params, id_dynInput, "false"));
add_config("dynTerm", str_or_n_value_lower(cell->params, id_dynTerm, "false"));
if (cell->type.in(id_OTP, id_ITP, id_IOTP)) {
add_config("termination", str_or_n_value(cell->params, ctx->id("termination"), "0"));
add_config("terminationReference", str_or_n_value(cell->params, ctx->id("terminationReference"), "VT"));
add_config("termination", str_or_n_value(cell->params, id_termination, "0"));
add_config("terminationReference", str_or_n_value(cell->params, id_terminationReference, "VT"));
}
close_instance();
std::string tile_name = uarch->tile_name(cell->bel.tile);
@ -304,41 +304,41 @@ struct BitstreamJsonBackend
void write_ddfr(CellInfo *cell) {
open_instance(cell);
add_config("dff_load", bool_or_default(cell->params, ctx->id("dff_load"), false));
add_config("dff_sync", bool_or_default(cell->params, ctx->id("dff_sync"), false));
add_config("dff_type", bool_or_default(cell->params, ctx->id("dff_type"), false));
add_config("iobname", str_or_default(cell->params, ctx->id("iobname"), ""));
add_config("path", int_or_default(cell->params, ctx->id("path"), 0));
add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
add_config("iobname", str_or_default(cell->params, id_iobname, ""));
add_config("path", int_or_default(cell->params, id_path, 0));
close_instance();
}
void write_dfr(CellInfo *cell) {
open_instance(cell);
add_config("data_inv", bool_or_default(cell->params, ctx->id("data_inv"), false));
add_config("dff_edge", bool_or_default(cell->params, ctx->id("dff_edge"), false));
add_config("dff_init", bool_or_default(cell->params, ctx->id("dff_init"), false));
add_config("dff_load", bool_or_default(cell->params, ctx->id("dff_load"), false));
add_config("dff_sync", bool_or_default(cell->params, ctx->id("dff_sync"), false));
add_config("dff_type", bool_or_default(cell->params, ctx->id("dff_type"), false));
add_config("mode", int_or_default(cell->params, ctx->id("mode"), 3));
add_config("iobname", str_or_default(cell->params, ctx->id("iobname"), ""));
add_config("data_inv", bool_or_default(cell->params, id_data_inv, false));
add_config("dff_edge", bool_or_default(cell->params, id_dff_edge, false));
add_config("dff_init", bool_or_default(cell->params, id_dff_init, false));
add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
add_config("mode", int_or_default(cell->params, id_mode, 3));
add_config("iobname", str_or_default(cell->params, id_iobname, ""));
close_instance();
}
void write_bfr(CellInfo *cell) {
open_instance(cell);
add_config("mode", int_or_default(cell->params, ctx->id("mode"), 2));
add_config("iobname", str_or_default(cell->params, ctx->id("iobname"), ""));
if (cell->params.count(ctx->id("data_inv"))) {
add_config("data_inv", bool_or_default(cell->params, ctx->id("data_inv"), false));
add_config("mode", int_or_default(cell->params, id_mode, 2));
add_config("iobname", str_or_default(cell->params, id_iobname, ""));
if (cell->params.count(id_data_inv)) {
add_config("data_inv", bool_or_default(cell->params, id_data_inv, false));
}
close_instance();
}
void write_cy(CellInfo *cell) {
open_instance(cell);
add_config("add_carry", int_or_default(cell->params, ctx->id("add_carry"), 0));
add_config("shifter", bool_or_default(cell->params, ctx->id("shifter"), false));
add_config("add_carry", int_or_default(cell->params, id_add_carry, 0));
add_config("shifter", bool_or_default(cell->params, id_shifter, false));
close_instance();
}
@ -349,15 +349,15 @@ struct BitstreamJsonBackend
close_instance();
}
if (bool_or_default(cell->params, id_dff_used)) {
std::string subtype = str_or_default(cell->params, ctx->id("type"), "DFF");
std::string subtype = str_or_default(cell->params, id_type, "DFF");
open_instance_fe(cell, subtype, ".DFF", "_D");
if (subtype =="DFF") {
add_config("dff_ctxt", std::to_string(int_or_default(cell->params, ctx->id("dff_ctxt"), 0)));
add_config("dff_edge", bool_or_default(cell->params, ctx->id("dff_edge"), false));
add_config("dff_init", bool_or_default(cell->params, ctx->id("dff_init"), false));
add_config("dff_load", bool_or_default(cell->params, ctx->id("dff_load"), false));
add_config("dff_sync", bool_or_default(cell->params, ctx->id("dff_sync"), false));
add_config("dff_type", bool_or_default(cell->params, ctx->id("dff_type"), false));
add_config("dff_ctxt", std::to_string(int_or_default(cell->params, id_dff_ctxt, 0)));
add_config("dff_edge", bool_or_default(cell->params, id_dff_edge, false));
add_config("dff_init", bool_or_default(cell->params, id_dff_init, false));
add_config("dff_load", bool_or_default(cell->params, id_dff_load, false));
add_config("dff_sync", bool_or_default(cell->params, id_dff_sync, false));
add_config("dff_type", bool_or_default(cell->params, id_dff_type, false));
}
close_instance();
}
@ -371,125 +371,125 @@ struct BitstreamJsonBackend
void write_iom(CellInfo *cell) {
open_instance(cell);
add_config("pads_path", str_or_default(cell->params, ctx->id("pads_path"), ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"));
add_config("pads_path", str_or_default(cell->params, id_pads_path, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;"));
close_instance();
}
void write_gck(CellInfo *cell) {
open_instance(cell);
add_config("inv_in", bool_or_default(cell->params, ctx->id("inv_in"), false));
add_config("inv_out", bool_or_default(cell->params, ctx->id("inv_out"), false));
add_config("std_mode", str_or_default(cell->params, ctx->id("std_mode"), "BYPASS"));
add_config("inv_in", bool_or_default(cell->params, id_inv_in, false));
add_config("inv_out", bool_or_default(cell->params, id_inv_out, false));
add_config("std_mode", str_or_default(cell->params, id_std_mode, "BYPASS"));
close_instance();
}
void write_wfb(CellInfo *cell) {
open_instance(cell);
add_config("delay_on", bool_or_default(cell->params, ctx->id("delay_on"), false));
add_config("delay", int_or_default(cell->params, ctx->id("delay"), 0));
add_config("wfg_edge", bool_or_default(cell->params, ctx->id("wfg_edge"), false));
add_config("delay_on", bool_or_default(cell->params, id_delay_on, false));
add_config("delay", int_or_default(cell->params, id_delay, 0));
add_config("wfg_edge", bool_or_default(cell->params, id_wfg_edge, false));
close_instance();
}
void write_wfg(CellInfo *cell) {
open_instance(cell);
add_config("mode", int_or_default(cell->params, ctx->id("mode"), 0));
add_config("delay_on", bool_or_default(cell->params, ctx->id("delay_on"), false));
add_config("delay", int_or_default(cell->params, ctx->id("delay"), 0));
add_config("wfg_edge", bool_or_default(cell->params, ctx->id("wfg_edge"), false));
add_config("pattern", extract_bits_or_default(cell->params, ctx->id("pattern"), 16));
add_config("pattern_end", int_or_default(cell->params, ctx->id("pattern_end"), 0));
add_config("div_ratio", int_or_default(cell->params, ctx->id("div_ratio"), 0));
add_config("div_phase", bool_or_default(cell->params, ctx->id("div_phase"), false));
add_config("reset_on_pll_lock_n", bool_or_default(cell->params, ctx->id("reset_on_pll_lock_n"), false));
add_config("reset_on_pll_locka_n", bool_or_default(cell->params, ctx->id("reset_on_pll_locka_n"), false));
add_config("reset_on_cal_lock_n", bool_or_default(cell->params, ctx->id("reset_on_cal_lock_n"), false));
add_config("mode", int_or_default(cell->params, id_mode, 0));
add_config("delay_on", bool_or_default(cell->params, id_delay_on, false));
add_config("delay", int_or_default(cell->params, id_delay, 0));
add_config("wfg_edge", bool_or_default(cell->params, id_wfg_edge, false));
add_config("pattern", extract_bits_or_default(cell->params, id_pattern, 16));
add_config("pattern_end", int_or_default(cell->params, id_pattern_end, 0));
add_config("div_ratio", int_or_default(cell->params, id_div_ratio, 0));
add_config("div_phase", bool_or_default(cell->params, id_div_phase, false));
add_config("reset_on_pll_lock_n", bool_or_default(cell->params, id_reset_on_pll_lock_n, false));
add_config("reset_on_pll_locka_n", bool_or_default(cell->params, id_reset_on_pll_locka_n, false));
add_config("reset_on_cal_lock_n", bool_or_default(cell->params, id_reset_on_cal_lock_n, false));
close_instance();
}
void write_pll(CellInfo *cell) {
open_instance(cell);
add_config("clk_outdiv1", extract_bits_or_default(cell->params, ctx->id("clk_outdiv1"), 3));
add_config("clk_outdiv2", extract_bits_or_default(cell->params, ctx->id("clk_outdiv2"), 3));
add_config("clk_outdiv3", extract_bits_or_default(cell->params, ctx->id("clk_outdiv3"), 3));
add_config("clk_outdiv4", extract_bits_or_default(cell->params, ctx->id("clk_outdiv4"), 3));
add_config("clk_outdivd1", extract_bits_or_default(cell->params, ctx->id("clk_outdivd1"), 4));
add_config("clk_outdivd2", extract_bits_or_default(cell->params, ctx->id("clk_outdivd2"), 4));
add_config("clk_outdivd3", extract_bits_or_default(cell->params, ctx->id("clk_outdivd3"), 4));
add_config("clk_outdivd4", extract_bits_or_default(cell->params, ctx->id("clk_outdivd4"), 4));
add_config("clk_outdivd5", extract_bits_or_default(cell->params, ctx->id("clk_outdivd5"), 4));
add_config("use_cal", bool_or_default(cell->params, ctx->id("use_cal"), false));
add_config("clk_cal_sel", extract_bits_or_default(cell->params, ctx->id("clk_cal_sel"), 2));
add_config("pll_odf", extract_bits_or_default(cell->params, ctx->id("pll_odf"), 2));
add_config("pll_lpf_res", extract_bits_or_default(cell->params, ctx->id("pll_lpf_res"), 4));
add_config("pll_lpf_cap", extract_bits_or_default(cell->params, ctx->id("pll_lpf_cap"), 4));
add_config("cal_div", extract_bits_or_default(cell->params, ctx->id("cal_div"), 4));
add_config("cal_delay", extract_bits_or_default(cell->params, ctx->id("cal_delay"), 6));
add_config("use_pll", bool_or_default(cell->params, ctx->id("use_pll"), true));
add_config("ref_intdiv", extract_bits_or_default(cell->params, ctx->id("ref_intdiv"), 5));
add_config("ref_osc_on", bool_or_default(cell->params, ctx->id("ref_osc_on"), false));
add_config("pll_cpump", extract_bits_or_default(cell->params, ctx->id("pll_cpump"), 4));
add_config("pll_lock", extract_bits_or_default(cell->params, ctx->id("pll_lock"), 4));
add_config("ext_fbk_on", bool_or_default(cell->params, ctx->id("ext_fbk_on"), false));
add_config("fbk_intdiv", extract_bits_or_default(cell->params, ctx->id("fbk_intdiv"), 7));
add_config("fbk_delay_on", bool_or_default(cell->params, ctx->id("fbk_delay_on"), false));
add_config("fbk_delay", extract_bits_or_default(cell->params, ctx->id("fbk_delay"), 6));
add_config("clk_outdiv1", extract_bits_or_default(cell->params, id_clk_outdiv1, 3));
add_config("clk_outdiv2", extract_bits_or_default(cell->params, id_clk_outdiv2, 3));
add_config("clk_outdiv3", extract_bits_or_default(cell->params, id_clk_outdiv3, 3));
add_config("clk_outdiv4", extract_bits_or_default(cell->params, id_clk_outdiv4, 3));
add_config("clk_outdivd1", extract_bits_or_default(cell->params, id_clk_outdivd1, 4));
add_config("clk_outdivd2", extract_bits_or_default(cell->params, id_clk_outdivd2, 4));
add_config("clk_outdivd3", extract_bits_or_default(cell->params, id_clk_outdivd3, 4));
add_config("clk_outdivd4", extract_bits_or_default(cell->params, id_clk_outdivd4, 4));
add_config("clk_outdivd5", extract_bits_or_default(cell->params, id_clk_outdivd5, 4));
add_config("use_cal", bool_or_default(cell->params, id_use_cal, false));
add_config("clk_cal_sel", extract_bits_or_default(cell->params, id_clk_cal_sel, 2));
add_config("pll_odf", extract_bits_or_default(cell->params, id_pll_odf, 2));
add_config("pll_lpf_res", extract_bits_or_default(cell->params, id_pll_lpf_res, 4));
add_config("pll_lpf_cap", extract_bits_or_default(cell->params, id_pll_lpf_cap, 4));
add_config("cal_div", extract_bits_or_default(cell->params, id_cal_div, 4));
add_config("cal_delay", extract_bits_or_default(cell->params, id_cal_delay, 6));
add_config("use_pll", bool_or_default(cell->params, id_use_pll, true));
add_config("ref_intdiv", extract_bits_or_default(cell->params, id_ref_intdiv, 5));
add_config("ref_osc_on", bool_or_default(cell->params, id_ref_osc_on, false));
add_config("pll_cpump", extract_bits_or_default(cell->params, id_pll_cpump, 4));
add_config("pll_lock", extract_bits_or_default(cell->params, id_pll_lock, 4));
add_config("ext_fbk_on", bool_or_default(cell->params, id_ext_fbk_on, false));
add_config("fbk_intdiv", extract_bits_or_default(cell->params, id_fbk_intdiv, 7));
add_config("fbk_delay_on", bool_or_default(cell->params, id_fbk_delay_on, false));
add_config("fbk_delay", extract_bits_or_default(cell->params, id_fbk_delay, 6));
close_instance();
}
void write_rfb(CellInfo *cell) {
open_instance(cell);
std::string context = str_or_default(cell->params, ctx->id("mem_ctxt"), "");
std::string context = str_or_default(cell->params, id_mem_ctxt, "");
if (!context.empty()) add_config("mem_ctxt", context);
add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false));
add_config("wck_edge", bool_or_default(cell->params, id_wck_edge, false));
close_instance();
}
void write_ram(CellInfo *cell) {
open_instance(cell);
add_config("mcka_edge", bool_or_default(cell->params, ctx->id("mcka_edge"), false));
add_config("mckb_edge", bool_or_default(cell->params, ctx->id("mckb_edge"), false));
add_config("pcka_edge", bool_or_default(cell->params, ctx->id("pcka_edge"), false));
add_config("pckb_edge", bool_or_default(cell->params, ctx->id("pckb_edge"), false));
add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 4));
add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 16));
std::string context = str_or_default(cell->params, ctx->id("mem_ctxt"), "");
add_config("mcka_edge", bool_or_default(cell->params, id_mcka_edge, false));
add_config("mckb_edge", bool_or_default(cell->params, id_mckb_edge, false));
add_config("pcka_edge", bool_or_default(cell->params, id_pcka_edge, false));
add_config("pckb_edge", bool_or_default(cell->params, id_pckb_edge, false));
add_config("raw_config0", extract_bits_or_default(cell->params, id_raw_config0, 4));
add_config("raw_config1", extract_bits_or_default(cell->params, id_raw_config1, 16));
std::string context = str_or_default(cell->params, id_mem_ctxt, "");
if (!context.empty()) add_config("mem_ctxt", context);
close_instance();
}
void write_dsp(CellInfo *cell) {
open_instance(cell);
add_config("raw_config0", extract_bits_or_default(cell->params, ctx->id("raw_config0"), 27));
add_config("raw_config1", extract_bits_or_default(cell->params, ctx->id("raw_config1"), 24));
add_config("raw_config2", extract_bits_or_default(cell->params, ctx->id("raw_config2"), 14));
add_config("raw_config3", extract_bits_or_default(cell->params, ctx->id("raw_config3"), 3));
add_config("raw_config0", extract_bits_or_default(cell->params, id_raw_config0, 27));
add_config("raw_config1", extract_bits_or_default(cell->params, id_raw_config1, 24));
add_config("raw_config2", extract_bits_or_default(cell->params, id_raw_config2, 14));
add_config("raw_config3", extract_bits_or_default(cell->params, id_raw_config3, 3));
close_instance();
}
void write_cdc(CellInfo *cell) {
open_instance(cell);
if (cell->type.in(id_DDE, id_TDE, id_CDC, id_XCDC)) {
add_config("ck0_edge", bool_or_default(cell->params, ctx->id("ck0_edge"), false));
add_config("ck1_edge", bool_or_default(cell->params, ctx->id("ck1_edge"), false));
add_config("ack_sel", bool_or_default(cell->params, ctx->id("ack_sel"), false));
add_config("bck_sel", bool_or_default(cell->params, ctx->id("bck_sel"), false));
add_config("use_adest_arst", bool_or_default(cell->params, ctx->id("use_adest_arst"), false));
add_config("use_bdest_arst", bool_or_default(cell->params, ctx->id("use_bdest_arst"), false));
add_config("ck0_edge", bool_or_default(cell->params, id_ck0_edge, false));
add_config("ck1_edge", bool_or_default(cell->params, id_ck1_edge, false));
add_config("ack_sel", bool_or_default(cell->params, id_ack_sel, false));
add_config("bck_sel", bool_or_default(cell->params, id_bck_sel, false));
add_config("use_adest_arst", bool_or_default(cell->params, id_use_adest_arst, false));
add_config("use_bdest_arst", bool_or_default(cell->params, id_use_bdest_arst, false));
if (cell->type != id_DDE) {
add_config("use_asrc_arst", bool_or_default(cell->params, ctx->id("use_asrc_arst"), false));
add_config("use_bsrc_arst", bool_or_default(cell->params, ctx->id("use_bsrc_arst"), false));
add_config("use_asrc_arst", bool_or_default(cell->params, id_use_asrc_arst, false));
add_config("use_bsrc_arst", bool_or_default(cell->params, id_use_bsrc_arst, false));
}
if (cell->type == id_XCDC) {
add_config("cck_sel", bool_or_default(cell->params, ctx->id("cck_sel"), false));
add_config("dck_sel", bool_or_default(cell->params, ctx->id("dck_sel"), false));
add_config("use_csrc_arst", bool_or_default(cell->params, ctx->id("use_csrc_arst"), false));
add_config("use_dsrc_arst", bool_or_default(cell->params, ctx->id("use_dsrc_arst"), false));
add_config("use_cdest_arst", bool_or_default(cell->params, ctx->id("use_cdest_arst"), false));
add_config("use_ddest_arst", bool_or_default(cell->params, ctx->id("use_ddest_arst"), false));
add_config("link_BA", bool_or_default(cell->params, ctx->id("link_BA"), false));
add_config("link_CB", bool_or_default(cell->params, ctx->id("link_CB"), false));
add_config("link_DC", bool_or_default(cell->params, ctx->id("link_DC"), false));
add_config("cck_sel", bool_or_default(cell->params, id_cck_sel, false));
add_config("dck_sel", bool_or_default(cell->params, id_dck_sel, false));
add_config("use_csrc_arst", bool_or_default(cell->params, id_use_csrc_arst, false));
add_config("use_dsrc_arst", bool_or_default(cell->params, id_use_dsrc_arst, false));
add_config("use_cdest_arst", bool_or_default(cell->params, id_use_cdest_arst, false));
add_config("use_ddest_arst", bool_or_default(cell->params, id_use_ddest_arst, false));
add_config("link_BA", bool_or_default(cell->params, id_link_BA, false));
add_config("link_CB", bool_or_default(cell->params, id_link_CB, false));
add_config("link_DC", bool_or_default(cell->params, id_link_DC, false));
}
}
close_instance();
@ -497,13 +497,13 @@ struct BitstreamJsonBackend
void write_fifo(CellInfo *cell) {
open_instance(cell);
add_config("rck_edge", bool_or_default(cell->params, ctx->id("rck_edge"), false));
add_config("wck_edge", bool_or_default(cell->params, ctx->id("wck_edge"), false));
add_config("rck_edge", bool_or_default(cell->params, id_rck_edge, false));
add_config("wck_edge", bool_or_default(cell->params, id_wck_edge, false));
if (cell->type != id_FIFO) {
add_config("use_read_arst", bool_or_default(cell->params, ctx->id("use_read_arst"), false));
add_config("use_write_arst", bool_or_default(cell->params, ctx->id("use_write_arst"), false));
add_config("use_read_arst", bool_or_default(cell->params, id_use_read_arst, false));
add_config("use_write_arst", bool_or_default(cell->params, id_use_write_arst, false));
}
add_config("read_addr_inv", extract_bits_or_default(cell->params, ctx->id("read_addr_inv"), 7));
add_config("read_addr_inv", extract_bits_or_default(cell->params, id_read_addr_inv, 7));
close_instance();
}
@ -518,7 +518,7 @@ struct BitstreamJsonBackend
PipId pip = w.second.pip;
const auto &pip_data = chip_pip_info(ctx->chip_info, w.second.pip);
const auto &extra_data = *reinterpret_cast<const NGUltraPipExtraDataPOD *>(pip_data.extra_data.get());
if (!extra_data.name or extra_data.type != PipExtra::PIP_EXTRA_INTERCONNECT) continue;
if (!extra_data.name || extra_data.type != PipExtra::PIP_EXTRA_INTERCONNECT) continue;
auto &pd = chip_pip_info(ctx->chip_info, pip);
IdString src = IdString(chip_tile_info(ctx->chip_info, pip.tile).wires[pd.src_wire].name);
std::string tile_name = uarch->tile_name(pip.tile);

13
himbaechel/uarch/ng-ultra/constids.inc
View File

@ -909,6 +909,8 @@ X(WEQ)
X(WRSTI1)
X(WRSTI2)
X(WRSTO)
X(WRSTI)
X(RRSTI)
// GBC
X(GBC)
@ -4525,6 +4527,7 @@ X(NX_CTX_U)
// NX_CY
X(NX_CY)
X(add_carry)
X(shifter)
// NX_DES
X(NX_DES)
@ -4565,6 +4568,9 @@ X(NX_DFR)
//X(path)
//X(ring)
// NX_DDFR_U
X(NX_DDFR_U)
// NX_DSP
X(NX_DSP)
X(raw_config0)
@ -6011,3 +6017,10 @@ X(LOC)
X(lut_used)
X(dff_used)
X(type)
// Timing
X(BEYOND_FE_LUT)
// csv
X(registered)

34
himbaechel/uarch/ng-ultra/csv.cc
View File

@ -209,25 +209,25 @@ void NgUltraImpl::parse_csv(const std::string &filename)
}
std::vector<CellInfo *> dest = get_cells(arg_iobname);
for (auto c : dest) {
c->params[ctx->id("iobname")] = arg_iobname;
c->params[ctx->id("location")] = arg_location;
c->params[ctx->id("standard")] = arg_standard;
c->params[ctx->id("drive")] = arg_drive;
c->params[ctx->id("slewRate")] = arg_slewRate;
c->params[ctx->id("inputDelayLine")] = arg_inputDelayLine;
c->params[ctx->id("outputDelayLine")] = arg_outputDelayLine;
c->params[ctx->id("inputDelayOn")] = std::string((std::stoi(arg_inputDelayLine)!=0) ? "True" : "False");
c->params[ctx->id("outputDelayOn")] = std::string((std::stoi(arg_outputDelayLine)!=0) ? "True" : "False");
c->params[ctx->id("differential")] = arg_differential;
c->params[ctx->id("weakTermination")] = arg_weakTermination;
c->params[id_iobname] = arg_iobname;
c->params[id_location] = arg_location;
c->params[id_standard] = arg_standard;
c->params[id_drive] = arg_drive;
c->params[id_slewRate] = arg_slewRate;
c->params[id_inputDelayLine] = arg_inputDelayLine;
c->params[id_outputDelayLine] = arg_outputDelayLine;
c->params[id_inputDelayOn] = std::string((std::stoi(arg_inputDelayLine)!=0) ? "True" : "False");
c->params[id_outputDelayOn] = std::string((std::stoi(arg_outputDelayLine)!=0) ? "True" : "False");
c->params[id_differential] = arg_differential;
c->params[id_weakTermination] = arg_weakTermination;
if (!arg_termination.empty()) {
c->params[ctx->id("termination")] = arg_termination;
c->params[ctx->id("terminationReference")] = arg_terminationReference;
c->params[id_termination] = arg_termination;
c->params[id_terminationReference] = arg_terminationReference;
}
c->params[ctx->id("turbo")] = arg_turbo;
c->params[ctx->id("inputSignalSlope")] = arg_inputSignalSlope;
c->params[ctx->id("outputCapacity")] = arg_outputCapacity;
c->params[ctx->id("registered")] = arg_registered;
c->params[id_turbo] = arg_turbo;
c->params[id_inputSignalSlope] = arg_inputSignalSlope;
c->params[id_outputCapacity] = arg_outputCapacity;
c->params[id_registered] = arg_registered;
}
if (dest.size()==0)
log_warning("Pad with name '%s' not found in netlist.\n", arg_iobname.c_str());

2
himbaechel/uarch/ng-ultra/gen/arch_gen.py
View File

@ -348,7 +348,7 @@ def create_tile_types(ch: Chip, bels, bel_pins, crossbars, interconnects, muxes,
if len(items)==1:
sub_type = tile_type
else:
sub_type = tile_type + "_"+str(num)
sub_type = f"{tile_type}_{num}"
tt = ch.create_tile_type(sub_type)
def lookup_site_wire(canon_name):

10
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -279,7 +279,7 @@ bool NgUltraImpl::update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip)
continue;
IdString dst = ctx->getWireName(ctx->getPipDstWire(pip2))[1];
if (boost::ends_with(dst.c_str(ctx),".DS")) {
cell->setParam(ctx->id("type"), Property("CSC"));
cell->setParam(id_type, Property("CSC"));
return true;
}
}
@ -303,7 +303,7 @@ bool NgUltraImpl::update_bff_to_scc(CellInfo *cell, BelId bel, PipId dst_pip)
continue;
IdString dst = ctx->getWireName(ctx->getPipSrcWire(pip2))[1];
if (boost::starts_with(dst.c_str(ctx),"SYSTEM.ST1")) {
cell->setParam(ctx->id("type"), Property("SCC"));
cell->setParam(id_type, Property("SCC"));
return true;
}
}
@ -339,7 +339,7 @@ void NgUltraImpl::postRoute()
case id_BEYOND_FE.index :
if (extra_data.input==0) {
// set bypass mode for DFF
cell->setParam(ctx->id("type"), Property("BFF"));
cell->setParam(id_type, Property("BFF"));
cell->params[id_dff_used] = Property(1,1);
// Note: no conflict, CSC and SCC modes are never available on same position
if (update_bff_to_csc(cell, bel, w.second.pip))
@ -358,7 +358,7 @@ void NgUltraImpl::postRoute()
cell->type = id_WFB;
break;
case id_GCK.index : gck_bypass++;
cell->setParam(ctx->id("std_mode"), extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
cell->setParam(id_std_mode, extra_data.input == 0 ? Property("BYPASS") : Property("CSC"));
break;
default:
log_error("Unmaped bel type '%s' for routing\n",type.c_str(ctx));
@ -479,7 +479,7 @@ struct SectionFEWorker
}
const auto &bel_data = chip_bel_info(ctx->chip_info, bel);
const auto &extra_data = *reinterpret_cast<const NGUltraBelExtraDataPOD *>(bel_data.extra_data.get());
std::string type = str_or_default(cell->params, ctx->id("type"), "");
std::string type = str_or_default(cell->params, id_type, "");
if (type=="CSC" && (extra_data.flags & BEL_EXTRA_FE_CSC) == 0) return false; // No CSC capability on FE
if (type=="SCC" && (extra_data.flags & BEL_EXTRA_FE_SCC) == 0) return false; // No SCC capability on FE
if (extra_data.flags & BEL_EXTRA_FE_CSC)

156
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -48,7 +48,7 @@ inline bool is_fe(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
inline bool is_dfr(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_NX_DFR; }
// Return true if a cell is a DDFR
inline bool is_ddfr(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("NX_DDFR_U"); }
inline bool is_ddfr(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_NX_DDFR_U; }
// Return true if a cell is a WFG/WFB
inline bool is_wfg(const BaseCtx *ctx, const CellInfo *cell) { return cell->type.in(id_WFB, id_WFG); }
@ -135,7 +135,7 @@ void NgUltraPacker::update_lut_init()
void NgUltraPacker::dff_rewrite(CellInfo *cell)
{
if (int_or_default(cell->params, ctx->id("dff_init"), 0)==0) {
if (int_or_default(cell->params, id_dff_init, 0)==0) {
// Reset not used
cell->disconnectPort(id_R);
} else {
@ -144,7 +144,7 @@ void NgUltraPacker::dff_rewrite(CellInfo *cell)
if (net) {
if (net->name == ctx->id("$PACKER_GND")) {
log_warning("Removing reset on '%s' since it is always 0.\n", cell->name.c_str(ctx));
cell->setParam(ctx->id("dff_init"), Property(0,1));
cell->setParam(id_dff_init, Property(0,1));
cell->disconnectPort(id_R);
} else if (net->name == ctx->id("$PACKER_VCC")) {
log_error("Invalid DFF configuration, reset on '%s' is always 1.\n", cell->name.c_str(ctx));
@ -152,7 +152,7 @@ void NgUltraPacker::dff_rewrite(CellInfo *cell)
}
}
if (int_or_default(cell->params, ctx->id("dff_load"), 0)==0) {
if (int_or_default(cell->params, id_dff_load, 0)==0) {
// Load not used
cell->disconnectPort(id_L);
} else {
@ -161,11 +161,11 @@ void NgUltraPacker::dff_rewrite(CellInfo *cell)
if (net) {
if (net->name == ctx->id("$PACKER_VCC")) {
log_warning("Removing load enable on '%s' since it is always 1.\n", cell->name.c_str(ctx));
cell->setParam(ctx->id("dff_load"), Property(0,0));
cell->setParam(id_dff_load, Property(0,0));
cell->disconnectPort(id_L);
} else if (net->name == ctx->id("$PACKER_GND")) {
log_warning("Converting to self loop, since load enable on '%s' is always 0.\n", cell->name.c_str(ctx));
cell->setParam(ctx->id("dff_load"), Property(0,0));
cell->setParam(id_dff_load, Property(0,0));
cell->disconnectPort(id_L);
cell->disconnectPort(id_I);
NetInfo *out = cell->getPort(id_O);
@ -178,7 +178,7 @@ void NgUltraPacker::dff_rewrite(CellInfo *cell)
void NgUltraPacker::ddfr_rewrite(CellInfo *cell)
{
// Reversed logic in comparison to DFF
if (int_or_default(cell->params, ctx->id("dff_load"), 0)==1) {
if (int_or_default(cell->params, id_dff_load, 0)==1) {
// Load not used
cell->disconnectPort(id_L);
} else {
@ -187,7 +187,7 @@ void NgUltraPacker::ddfr_rewrite(CellInfo *cell)
if (net) {
if (net->name == ctx->id("$PACKER_VCC")) {
log_warning("Removing load enable on '%s' since it is always 1.\n", cell->name.c_str(ctx));
cell->setParam(ctx->id("dff_load"), Property(0,0));
cell->setParam(id_dff_load, Property(0,0));
cell->disconnectPort(id_L);
}
}
@ -271,7 +271,7 @@ void NgUltraPacker::lut_to_fe(CellInfo *lut, CellInfo *fe, bool no_dff, Property
lut->movePortTo(id_I4, fe, id_I4);
lut->movePortTo(id_O, fe, id_LO);
if (no_dff) {
fe->timing_index = ctx->get_cell_timing_idx(ctx->id("BEYOND_FE_LUT"));
fe->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
}
}
@ -295,20 +295,20 @@ void NgUltraPacker::dff_to_fe(CellInfo *dff, CellInfo *fe, bool pass_thru_lut)
fe->params[id_dff_used] = Property(1,1);
dff->movePortTo(id_O, fe, id_DO);
if (dff->type == id_NX_BFF) {
fe->setParam(ctx->id("type"), Property("BFF"));
fe->setParam(id_type, Property("BFF"));
} else {
fe->setParam(ctx->id("type"), Property("DFF"));
fe->setParam(id_type, Property("DFF"));
dff->movePortTo(id_R, fe, id_R);
dff->movePortTo(id_CK, fe, id_CK);
dff->movePortTo(id_L, fe, id_L);
if (dff->params.count(ctx->id("dff_ctxt"))) fe->setParam(ctx->id("dff_ctxt"),dff->params[ctx->id("dff_ctxt")]);
if (dff->params.count(ctx->id("dff_edge"))) fe->setParam(ctx->id("dff_edge"),dff->params[ctx->id("dff_edge")]);
if (dff->params.count(ctx->id("dff_init"))) fe->setParam(ctx->id("dff_init"),dff->params[ctx->id("dff_init")]);
if (dff->params.count(ctx->id("dff_load"))) fe->setParam(ctx->id("dff_load"),dff->params[ctx->id("dff_load")]);
if (dff->params.count(ctx->id("dff_sync"))) fe->setParam(ctx->id("dff_sync"),dff->params[ctx->id("dff_sync")]);
if (dff->params.count(ctx->id("dff_type"))) fe->setParam(ctx->id("dff_type"),dff->params[ctx->id("dff_type")]);
if (dff->params.count(id_dff_ctxt)) fe->setParam(id_dff_ctxt,dff->params[id_dff_ctxt]);
if (dff->params.count(id_dff_edge)) fe->setParam(id_dff_edge,dff->params[id_dff_edge]);
if (dff->params.count(id_dff_init)) fe->setParam(id_dff_init,dff->params[id_dff_init]);
if (dff->params.count(id_dff_load)) fe->setParam(id_dff_load,dff->params[id_dff_load]);
if (dff->params.count(id_dff_sync)) fe->setParam(id_dff_sync,dff->params[id_dff_sync]);
if (dff->params.count(id_dff_type)) fe->setParam(id_dff_type,dff->params[id_dff_type]);
}
if (pass_thru_lut) {
NetInfo *new_out = ctx->createNet(ctx->id(dff->name.str(ctx) + "$LO"));
@ -390,7 +390,7 @@ void NgUltraPacker::pack_xluts(void)
lut_and_ff++;
orig_dff = nullptr;
} else {
lut[i]->timing_index = ctx->get_cell_timing_idx(ctx->id("BEYOND_FE_LUT"));
lut[i]->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
lut_only++;
}
} else {
@ -402,7 +402,7 @@ void NgUltraPacker::pack_xluts(void)
packed_cells.insert(dff->name);
lut_and_ff++;
} else {
lut[i]->timing_index = ctx->get_cell_timing_idx(ctx->id("BEYOND_FE_LUT"));
lut[i]->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
lut_only++;
}
}
@ -553,7 +553,7 @@ void NgUltraPacker::pack_lut_multi_dffs(void)
if (use_bff) {
CellInfo *new_cell = create_cell_ptr(id_BEYOND_FE, ctx->id(ci.name.str(ctx) + "$bff"));
new_cell->params[id_dff_used] = Property(1,1);
new_cell->setParam(ctx->id("type"), Property("BFF"));
new_cell->setParam(id_type, Property("BFF"));
new_cell->connectPort(id_DI, o);
root->constr_children.push_back(new_cell);
new_cell->cluster = root->cluster;
@ -779,24 +779,24 @@ void NgUltraPacker::pack_iobs(void)
bfr_added++;
iod = create_cell_ptr(id_BFR, ctx->id(cell->name.str(ctx) + "$iod_cd"));
NetInfo *new_out = ctx->createNet(ctx->id(iod->name.str(ctx) + "$O"));
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
cell->disconnectPort(id_C);
if (c_net->name == ctx->id("$PACKER_GND"))
iod->setParam(ctx->id("mode"), Property(0, 2));
iod->setParam(id_mode, Property(0, 2));
else if (c_net->name == ctx->id("$PACKER_VCC"))
iod->setParam(ctx->id("mode"), Property(1, 2));
iod->setParam(id_mode, Property(1, 2));
else {
iod->connectPort(id_I, c_net);
iod->setParam(ctx->id("mode"), Property(2, 2));
iod->setParam(ctx->id("data_inv"), Property(0, 1));
iod->setParam(id_mode, Property(2, 2));
iod->setParam(id_data_inv, Property(0, 1));
}
iod->connectPort(id_O, new_out);
cell->connectPort(id_C,new_out);
} else {
ddfr_added++;
iod->type = id_DDFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(ctx->id("path"), Property(2, 2));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
iod->setParam(id_path, Property(2, 2));
ddfr_rewrite(iod);
disconnect_unused(iod, id_O2);
disconnect_if_gnd(iod, id_L);
@ -805,7 +805,7 @@ void NgUltraPacker::pack_iobs(void)
} else {
dfr_added++;
iod->type = id_DFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
dff_rewrite(iod);
}
Loc cd_loc = cell->getLocation();
@ -826,24 +826,24 @@ void NgUltraPacker::pack_iobs(void)
bfr_added++;
iod = create_cell_ptr(id_BFR, ctx->id(cell->name.str(ctx) + "$iod_od"));
NetInfo *new_out = ctx->createNet(ctx->id(iod->name.str(ctx) + "$O"));
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
cell->disconnectPort(id_I);
if (i_net->name == ctx->id("$PACKER_GND"))
iod->setParam(ctx->id("mode"), Property(0, 2));
iod->setParam(id_mode, Property(0, 2));
else if (i_net->name == ctx->id("$PACKER_VCC"))
iod->setParam(ctx->id("mode"), Property(1, 2));
iod->setParam(id_mode, Property(1, 2));
else {
iod->connectPort(id_I, i_net);
iod->setParam(ctx->id("mode"), Property(2, 2));
iod->setParam(ctx->id("data_inv"), Property(0, 1));
iod->setParam(id_mode, Property(2, 2));
iod->setParam(id_data_inv, Property(0, 1));
}
iod->connectPort(id_O, new_out);
cell->connectPort(id_I,new_out);
} else {
ddfr_added++;
iod->type = id_DDFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(ctx->id("path"), Property(0, 2));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
iod->setParam(id_path, Property(0, 2));
ddfr_rewrite(iod);
disconnect_unused(iod, id_O2);
disconnect_if_gnd(iod, id_L);
@ -852,7 +852,7 @@ void NgUltraPacker::pack_iobs(void)
} else {
dfr_added++;
iod->type = id_DFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
dff_rewrite(iod);
}
Loc cd_loc = cell->getLocation();
@ -873,11 +873,11 @@ void NgUltraPacker::pack_iobs(void)
bfr_added++;
iod = create_cell_ptr(id_BFR, ctx->id(cell->name.str(ctx) + "$iod_id"));
NetInfo *new_in = ctx->createNet(ctx->id(iod->name.str(ctx) + "$I"));
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
cell->disconnectPort(id_O);
iod->connectPort(id_O, o_net);
iod->setParam(ctx->id("mode"), Property(2, 2));
iod->setParam(ctx->id("data_inv"), Property(0, 1));
iod->setParam(id_mode, Property(2, 2));
iod->setParam(id_data_inv, Property(0, 1));
iod->connectPort(id_I, new_in);
cell->connectPort(id_O,new_in);
bfr_mode = true;
@ -885,8 +885,8 @@ void NgUltraPacker::pack_iobs(void)
ddfr_mode = true;
ddfr_added++;
iod->type = id_DDFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(ctx->id("path"), Property(1, 2));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
iod->setParam(id_path, Property(1, 2));
ddfr_rewrite(iod);
disconnect_if_gnd(iod, id_I2);
disconnect_if_gnd(iod, id_L);
@ -895,7 +895,7 @@ void NgUltraPacker::pack_iobs(void)
} else {
dfr_added++;
iod->type = id_DFR;
iod->setParam(ctx->id("iobname"),str_or_default(cell->params, ctx->id("iobname"), ""));
iod->setParam(id_iobname,str_or_default(cell->params, id_iobname, ""));
dff_rewrite(iod);
}
Loc cd_loc = cell->getLocation();
@ -979,25 +979,13 @@ void NgUltraPacker::pack_cy_input_and_output(CellInfo *cy, IdString cluster, IdS
fe->connectPort(id_LO, new_out);
cy->connectPort(in_port, new_out);
} else {
// TODO: This is too constrained, since makes rest of logic
// separated from input
/*
CellInfo *lut = net_driven_by(ctx, net, is_lut, id_O);
if (lut && net->users.entries()==1) {
if (!lut->params.count(id_lut_table))
log_error("Cell '%s' missing lut_table\n", lut->name.c_str(ctx));
lut_to_fe(lut, fe, false, lut->params[id_lut_table]);
packed_cells.insert(lut->name);
} else {
*/
fe->params[id_lut_table] = Property(0xaaaa, 16);
fe->params[id_lut_used] = Property(1,1);
cy->disconnectPort(in_port);
NetInfo *new_out = ctx->createNet(ctx->id(fe->name.str(ctx) + "$o"));
fe->connectPort(id_I1, net);
fe->connectPort(id_LO, new_out);
cy->connectPort(in_port, new_out);
//}
fe->params[id_lut_table] = Property(0xaaaa, 16);
fe->params[id_lut_used] = Property(1,1);
cy->disconnectPort(in_port);
NetInfo *new_out = ctx->createNet(ctx->id(fe->name.str(ctx) + "$o"));
fe->connectPort(id_I1, net);
fe->connectPort(id_LO, new_out);
cy->connectPort(in_port, new_out);
}
lut_only++;
}
@ -1014,7 +1002,7 @@ void NgUltraPacker::pack_cy_input_and_output(CellInfo *cy, IdString cluster, IdS
} else
dff_only++;
} else {
fe->timing_index = ctx->get_cell_timing_idx(ctx->id("BEYOND_FE_LUT"));
fe->timing_index = ctx->get_cell_timing_idx(id_BEYOND_FE_LUT);
}
fe->cluster = cluster;
fe->constr_z = placer;
@ -1344,7 +1332,7 @@ void NgUltraPacker::pack_cdcs(void)
CellInfo &ci = *cell.second;
if (!ci.type.in(id_NX_CDC_U))
continue;
int mode = int_or_default(ci.params, ctx->id("mode"), 0);
int mode = int_or_default(ci.params, id_mode, 0);
switch(mode) {
case 0 : ci.type = id_DDE; break;
case 1 : ci.type = id_TDE; break;
@ -1456,7 +1444,7 @@ void NgUltraPacker::pack_fifos(void)
CellInfo &ci = *cell.second;
if (!ci.type.in(id_NX_FIFO_U))
continue;
int mode = int_or_default(ci.params, ctx->id("mode"), 0);
int mode = int_or_default(ci.params, id_mode, 0);
switch(mode) {
case 0 : ci.type = id_FIFO; break;
case 1 : ci.type = id_XHFIFO; break;
@ -1465,8 +1453,8 @@ void NgUltraPacker::pack_fifos(void)
log_error("Unknown mode %d for cell '%s'.\n", mode, ci.name.c_str(ctx));
}
ci.cluster = ci.name;
bool use_write_arst = bool_or_default(ci.params, ctx->id("use_write_arst"), false);
bool use_read_arst = bool_or_default(ci.params, ctx->id("use_read_arst"), false);
bool use_write_arst = bool_or_default(ci.params, id_use_write_arst, false);
bool use_read_arst = bool_or_default(ci.params, id_use_read_arst, false);
int rsti = (ci.type == id_FIFO) ? 2 : 4;
for (int i=1;i<=rsti;i++) {
@ -1479,7 +1467,7 @@ void NgUltraPacker::pack_fifos(void)
}
if (use_write_arst) {
IdString port = ctx->idf("WRSTI");
IdString port = id_WRSTI;
connect_gnd_if_unconnected(&ci, port);
NetInfo *wrsti_net = ci.getPort(port);
ci.disconnectPort(port);
@ -1493,10 +1481,10 @@ void NgUltraPacker::pack_fifos(void)
pack_xrf_input_and_output(&ci, ci.name, id_WRSTI4, IdString(), PLACE_FIFO_WRSTI4, lut_only, lut_and_ff, dff_only);
}
} else {
disconnect_unused(&ci,ctx->id("WRSTI"));
disconnect_unused(&ci,id_WRSTI);
}
if (use_read_arst) {
IdString port = ctx->idf("RRSTI");
IdString port = id_RRSTI;
connect_gnd_if_unconnected(&ci, port);
NetInfo *rrsti_net = ci.getPort(port);
ci.disconnectPort(port);
@ -1510,7 +1498,7 @@ void NgUltraPacker::pack_fifos(void)
pack_xrf_input_and_output(&ci, ci.name, id_RRSTI4, IdString(), PLACE_FIFO_RRSTI4, lut_only, lut_and_ff, dff_only);
}
} else {
disconnect_unused(&ci,ctx->id("RRSTI"));
disconnect_unused(&ci,id_RRSTI);
}
for (int i = 1; i <= 18; i++) {
@ -1556,12 +1544,12 @@ void NgUltraPacker::pack_fifos(void)
if (mode==0) {
// FIFO
ci.renamePort(id_WEQ1, ctx->id("WEQ"));
pack_xrf_input_and_output(&ci, ci.name, IdString(), ctx->id("WEQ"), PLACE_FIFO_WEQ1, lut_only, lut_and_ff, dff_only);
ci.renamePort(id_WEQ1, id_WEQ);
pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ, PLACE_FIFO_WEQ1, lut_only, lut_and_ff, dff_only);
disconnect_unused(&ci, id_WEQ2);
ci.renamePort(id_REQ1, ctx->id("REQ"));
pack_xrf_input_and_output(&ci, ci.name, IdString(), ctx->id("REQ"), PLACE_FIFO_REQ1, lut_only, lut_and_ff, dff_only);
ci.renamePort(id_REQ1, id_REQ);
pack_xrf_input_and_output(&ci, ci.name, IdString(), id_REQ, PLACE_FIFO_REQ1, lut_only, lut_and_ff, dff_only);
disconnect_unused(&ci, id_REQ2);
} else {
pack_xrf_input_and_output(&ci, ci.name, IdString(), id_WEQ1, PLACE_FIFO_WEQ1, lut_only, lut_and_ff, dff_only);
@ -1642,7 +1630,7 @@ void NgUltraPacker::insert_ioms()
CellInfo *iom = nullptr;
IdString port = uarch->global_capable_bels.at(iotp_bel);
CellInfo *input_pad = ctx->getBoundBelCell(iotp_bel);
std::string iobname = str_or_default(input_pad->params, ctx->id("iobname"), "");
std::string iobname = str_or_default(input_pad->params, id_iobname, "");
if (!ctx->checkBelAvail(bel)) {
iom = ctx->getBoundBelCell(bel);
log_info(" Reusing IOM in bank '%s' for signal '%s'\n", iob.c_str(ctx), iobname.c_str());
@ -1796,7 +1784,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port)
void NgUltraPacker::constrain_location(CellInfo *cell)
{
std::string location = str_or_default(cell->params, ctx->id("location"), "");
std::string location = str_or_default(cell->params, id_location, "");
if (!location.empty()) {
if (uarch->locations.count(location)) {
BelId bel = uarch->locations[location];
@ -1848,7 +1836,7 @@ void NgUltraPacker::pack_wfgs(void)
continue;
ci.type = id_WFG;
constrain_location(&ci);
int mode = int_or_default(ci.params, ctx->id("mode"), 1);
int mode = int_or_default(ci.params, id_mode, 1);
if (mode == 0) { // WFB - bypass mode
ci.type = id_WFB;
// must not be used, zero is tollerated
@ -1882,7 +1870,7 @@ void NgUltraPacker::pack_gcks(void)
if (!ci.type.in(id_NX_GCK_U))
continue;
ci.type = id_GCK;
std::string mode = str_or_default(ci.params, ctx->id("std_mode"), "BYPASS");
std::string mode = str_or_default(ci.params, id_std_mode, "BYPASS");
if (mode == "BYPASS") {
disconnect_unused(&ci, id_SI2);
disconnect_unused(&ci, id_CMD);
@ -2306,7 +2294,7 @@ void NgUltraPacker::pre_place(void)
if (bfr->type.in(id_BFR,id_DFR,id_DDFR)) {
CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$csc", bfr->name.c_str(ctx)));
gck_cell->params[id_std_mode] = Property("CSC");
gck_cell->params[ctx->id("inv_out")] = Property(true);
gck_cell->params[id_inv_out] = Property(true);
NetInfo *old_out = fe->getPort(id_LO);
NetInfo *old_in = fe->getPort(id_I1);
fe->disconnectPort(id_LO);
@ -2346,7 +2334,7 @@ void NgUltraImpl::postPlace()
const auto &extra_data = *reinterpret_cast<const NGUltraBelExtraDataPOD *>(bel_data.extra_data.get());
// Check if CSC mode only if FE is capable
if ((extra_data.flags & BEL_EXTRA_FE_CSC)) {
if (str_or_default(ci.params, ctx->id("type"), "")=="CSC") continue;
if (str_or_default(ci.params, id_type, "")=="CSC") continue;
// Disable routing to S output if CSC is not used
disable_beyond_fe_s_output(ci.bel);
}
@ -2455,8 +2443,8 @@ void NgUltraPacker::insert_csc()
ctx->unbindBel(cell->bel);
cell->disconnectPort(id_LO);
NetInfo *new_out = ctx->createNet(ctx->id(cell->name.str(ctx) + "$o"));
cell->params[ctx->id("CSC")] = Property(Property::State::S1);
cell->params[ctx->id("type")] = Property("CSC");
cell->params[id_CSC] = Property(Property::State::S1);
cell->params[id_type] = Property("CSC");
cell->params[id_dff_used] = Property(1,1);
cell->connectPort(id_LO,new_out);
cell->connectPort(id_DI,new_out);
@ -2476,8 +2464,8 @@ void NgUltraPacker::insert_csc()
NetInfo *new_out = ctx->createNet(ctx->id(fe->name.str(ctx) + "$o"));
fe->params[id_lut_table] = Property(0xaaaa, 16);
fe->params[id_lut_used] = Property(1,1);
fe->params[ctx->id("CSC")] = Property(Property::State::S1);
fe->params[ctx->id("type")] = Property("CSC");
fe->params[id_CSC] = Property(Property::State::S1);
fe->params[id_type] = Property("CSC");
fe->params[id_dff_used] = Property(1,1);
fe->connectPort(id_I1, net);
fe->connectPort(id_DO,new_out);