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nexus: Add timing data for LRAM

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-08-10 15:47:22 +01:00
parent 66722096ed
commit f7354d092d
3 changed files with 30 additions and 0 deletions
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16
nexus/arch.cc
View File

@ -543,6 +543,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
return TMG_CLOCK_INPUT;
clockInfoCount = 1;
return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
} else if (cell->type == id_LRAM_CORE) {
if (port.in(id_OPCGLDCK, id_OPCGLOADCLK, id_SCANCLK, id_SCANRST, id_TBISTN, id_INITN, id_STDBYN, id_IGN,
id_DPS))
return TMG_IGNORE;
if (port == id_CLK)
return TMG_CLOCK_INPUT;
clockInfoCount = 1;
return (cell->ports.at(port).type == PORT_IN) ? TMG_REGISTER_INPUT : TMG_REGISTER_OUTPUT;
} else if (cell->type == id_MULT18_CORE || cell->type == id_MULT18X36_CORE || cell->type == id_MULT36_CORE) {
return (cell->ports.at(port).type == PORT_IN) ? TMG_COMB_INPUT : TMG_COMB_OUTPUT;
} else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
@ -602,6 +610,14 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
}
// Lookup edge based on inversion
info.edge = (get_cell_pinmux(cell, info.clock_port) == PINMUX_INV) ? FALLING_EDGE : RISING_EDGE;
} else if (cell->type == id_LRAM_CORE) {
info.clock_port = id_CLK;
if (cell->ports.at(port).type == PORT_IN) {
lookup_cell_setuphold(cell->tmg_index, lookup_port(port), id_CLK, info.setup, info.hold);
} else {
NPNR_ASSERT(lookup_cell_delay(cell->tmg_index, id_CLK, lookup_port(port), info.clockToQ));
}
info.edge = (get_cell_pinmux(cell, info.clock_port) == PINMUX_INV) ? FALLING_EDGE : RISING_EDGE;
} else if (cell->type == id_PREADD9_CORE || cell->type == id_REG18_CORE || cell->type == id_MULT9_CORE) {
info.clock_port = id_CLK;
if (cell->ports.at(port).type == PORT_IN) {

1
nexus/constids.inc
View File

@ -465,6 +465,7 @@ X(TBISTN)
X(WE)
X(CEOUTA)
X(CEOUTB)
X(OPCGLOADCLK)
X(MULTADDSUB9X9WIDE)
X(MULTADDSUB18X18WIDE)

13
nexus/pack.cc
View File

@ -2614,6 +2614,19 @@ void Arch::assignCellInfo(CellInfo *cell)
cell->tmg_index = get_cell_timing_idx(id(str_or_default(cell->params, id_MODE, "DP16K") + "_MODE"));
NPNR_ASSERT(cell->tmg_index != -1);
} else if (cell->type == id_LRAM_CORE) {
// Strip off bus indices to get the timing ports
// as timing is generally word-wide
for (const auto &port : cell->ports) {
const std::string &name = port.first.str(this);
size_t idx_end = name.find_last_not_of("0123456789");
std::string base = name.substr(0, idx_end + 1);
// Strip off bus index
cell->tmg_portmap[port.first] = id(base);
}
cell->tmg_index = get_cell_timing_idx(id_LRAM_CORE);
NPNR_ASSERT(cell->tmg_index != -1);
} else if (is_dsp_cell(cell)) {
// Strip off bus indices to get the timing ports
// as timing is generally word-wide