gowin: Himbaechel, fix style
Run clang-format Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit
myrtle
parent
e4d2e1bd85
commit
f7fbe0db04
@ -7,230 +7,234 @@
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NEXTPNR_NAMESPACE_BEGIN
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void GowinImpl::init(Context *ctx) {
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h.init(ctx);
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HimbaechelAPI::init(ctx);
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// These fields go in the header of the output JSON file and can help
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// gowin_pack support different architectures
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ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
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// XXX it would be nice to write chip/base name in the header as well,
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// but maybe that will come up when there is clarity with
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// Arch::archArgsToId
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void GowinImpl::init(Context *ctx)
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{
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h.init(ctx);
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HimbaechelAPI::init(ctx);
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// These fields go in the header of the output JSON file and can help
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// gowin_pack support different architectures
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ctx->settings[ctx->id("packer.arch")] = std::string("himbaechel/gowin");
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// XXX it would be nice to write chip/base name in the header as well,
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// but maybe that will come up when there is clarity with
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// Arch::archArgsToId
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}
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void GowinImpl::prePlace() {
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ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
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ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
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ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
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assign_cell_info();
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void GowinImpl::prePlace()
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{
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ctx->cells.at(ctx->id("leds_OBUF_O"))->setAttr(ctx->id("BEL"), std::string("X0Y14/IOBA"));
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ctx->cells.at(ctx->id("leds_OBUF_O_1"))->setAttr(ctx->id("BEL"), std::string("X0Y15/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_2"))->setAttr(ctx->id("BEL"), std::string("X0Y20/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_3"))->setAttr(ctx->id("BEL"), std::string("X0Y21/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_4"))->setAttr(ctx->id("BEL"), std::string("X0Y24/IOBB"));
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ctx->cells.at(ctx->id("leds_OBUF_O_5"))->setAttr(ctx->id("BEL"), std::string("X0Y25/IOBB"));
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ctx->cells.at(ctx->id("rst_IBUF_I"))->setAttr(ctx->id("BEL"), std::string("X0Y4/IOBA"));
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assign_cell_info();
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}
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void GowinImpl::pack() {
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_IBUF, id_I),
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CellTypePort(id_OBUF, id_O),
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};
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h.remove_nextpnr_iobs(top_ports);
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// Replace constants with LUTs
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const dict<IdString, Property> vcc_params;
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const dict<IdString, Property> gnd_params;
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h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
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void GowinImpl::pack()
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{
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// Trim nextpnr IOBs - assume IO buffer insertion has been done in synthesis
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const pool<CellTypePort> top_ports{
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CellTypePort(id_IBUF, id_I),
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CellTypePort(id_OBUF, id_O),
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};
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h.remove_nextpnr_iobs(top_ports);
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// Replace constants with LUTs
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const dict<IdString, Property> vcc_params;
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const dict<IdString, Property> gnd_params;
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h.replace_constants(CellTypePort(id_GOWIN_VCC, id_V), CellTypePort(id_GOWIN_GND, id_G), vcc_params, gnd_params);
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// disconnect the constant LUT inputs
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mod_lut_inputs();
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// disconnect the constant LUT inputs
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mod_lut_inputs();
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// Constrain directly connected LUTs and FFs together to use dedicated resources
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int lutffs = h.constrain_cell_pairs(
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pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
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pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
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{id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
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{id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
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{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
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{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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// Constrain directly connected LUTs and FFs together to use dedicated resources
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int lutffs = h.constrain_cell_pairs(
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pool<CellTypePort>{{id_LUT1, id_F}, {id_LUT2, id_F}, {id_LUT3, id_F}, {id_LUT4, id_F}},
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pool<CellTypePort>{{id_DFF, id_D}, {id_DFFE, id_D}, {id_DFFN, id_D}, {id_DFFNE, id_D},
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{id_DFFS, id_D}, {id_DFFSE, id_D}, {id_DFFNS, id_D}, {id_DFFNSE, id_D},
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{id_DFFR, id_D}, {id_DFFRE, id_D}, {id_DFFNR, id_D}, {id_DFFNRE, id_D},
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{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
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{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}},
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1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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}
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bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const {
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Loc l = ctx->getBelLocation(bel);
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if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
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return slice_valid(l.x, l.y, l.z / 2);
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} else {
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return true;
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}
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bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
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{
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Loc l = ctx->getBelLocation(bel);
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if (ctx->getBelType(bel).in(id_LUT4, id_DFF)) {
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return slice_valid(l.x, l.y, l.z / 2);
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} else {
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return true;
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}
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}
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// Bel bucket functions
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IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const {
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if (cell_type.in(id_IBUF, id_OBUF)) {
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return id_IOB;
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}
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if (type_is_lut(cell_type)) {
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return id_LUT4;
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}
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if (type_is_dff(cell_type)) {
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return id_DFF;
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}
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if (cell_type == id_GOWIN_GND) {
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return id_GND;
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}
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if (cell_type == id_GOWIN_VCC) {
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return id_VCC;
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}
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return cell_type;
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IdString GowinImpl::getBelBucketForCellType(IdString cell_type) const
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{
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if (cell_type.in(id_IBUF, id_OBUF)) {
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return id_IOB;
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}
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if (type_is_lut(cell_type)) {
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return id_LUT4;
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}
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if (type_is_dff(cell_type)) {
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return id_DFF;
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}
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if (cell_type == id_GOWIN_GND) {
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return id_GND;
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}
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if (cell_type == id_GOWIN_VCC) {
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return id_VCC;
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}
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return cell_type;
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}
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bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const {
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB) {
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return cell_type.in(id_IBUF, id_OBUF);
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}
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if (bel_type == id_LUT4) {
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return type_is_lut(cell_type);
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}
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if (bel_type == id_DFF) {
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return type_is_dff(cell_type);
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}
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if (bel_type == id_GND) {
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return cell_type == id_GOWIN_GND;
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}
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if (bel_type == id_VCC) {
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return cell_type == id_GOWIN_VCC;
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}
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return (bel_type == cell_type);
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bool GowinImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
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{
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IdString bel_type = ctx->getBelType(bel);
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if (bel_type == id_IOB) {
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return cell_type.in(id_IBUF, id_OBUF);
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}
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if (bel_type == id_LUT4) {
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return type_is_lut(cell_type);
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}
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if (bel_type == id_DFF) {
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return type_is_dff(cell_type);
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}
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if (bel_type == id_GND) {
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return cell_type == id_GOWIN_GND;
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}
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if (bel_type == id_VCC) {
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return cell_type == id_GOWIN_VCC;
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}
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return (bel_type == cell_type);
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}
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void GowinImpl::assign_cell_info() {
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (is_lut(ci)) {
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fc.lut_f = ci->getPort(id_F);
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} else if (is_dff(ci)) {
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fc.ff_d = ci->getPort(id_D);
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fc.ff_clk = ci->getPort(id_CLK);
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fc.ff_ce = ci->getPort(id_CE);
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for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
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fc.ff_lsr = ci->getPort(port);
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if (fc.ff_lsr != nullptr) {
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break;
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}
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}
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}
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}
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void GowinImpl::assign_cell_info()
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{
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fast_cell_info.resize(ctx->cells.size());
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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auto &fc = fast_cell_info.at(ci->flat_index);
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if (is_lut(ci)) {
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fc.lut_f = ci->getPort(id_F);
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} else if (is_dff(ci)) {
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fc.ff_d = ci->getPort(id_D);
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fc.ff_clk = ci->getPort(id_CLK);
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fc.ff_ce = ci->getPort(id_CE);
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for (IdString port : {id_SET, id_RESET, id_PRESET, id_CLEAR}) {
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fc.ff_lsr = ci->getPort(port);
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if (fc.ff_lsr != nullptr) {
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break;
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}
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}
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}
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}
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}
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bool GowinImpl::slice_valid(int x, int y, int z) const {
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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if (!ff) {
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return true; // always valid if only LUT used
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}
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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if (lut) {
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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if (ff_data.ff_d != lut_data.lut_f)
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return false;
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}
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int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
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const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
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if (adj_ff == nullptr) {
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return true;
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}
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// DFFs must be same type or compatible
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if (ff->type != adj_ff->type &&
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( (ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR))
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|| (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS))
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|| (ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE))
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|| (ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE))
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|| (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC))
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|| (ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP))
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|| (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE))
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|| (ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE))
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|| (ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR))
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|| (ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS))
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|| (ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE))
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|| (ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE))
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|| (ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC))
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|| (ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP))
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|| (ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE))
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|| (ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE))
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)) {
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return false;
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}
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bool GowinImpl::slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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if (!ff) {
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return true; // always valid if only LUT used
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}
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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if (lut) {
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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if (ff_data.ff_d != lut_data.lut_f)
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return false;
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}
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int adj_z = (1 - (z & 1) * 2 + z) * 2 + 1;
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const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_z)));
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if (adj_ff == nullptr) {
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return true;
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}
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// DFFs must be same type or compatible
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if (ff->type != adj_ff->type &&
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((ff->type.in(id_DFFS) && !adj_ff->type.in(id_DFFR)) || (ff->type.in(id_DFFR) && !adj_ff->type.in(id_DFFS)) ||
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(ff->type.in(id_DFFSE) && !adj_ff->type.in(id_DFFRE)) ||
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(ff->type.in(id_DFFRE) && !adj_ff->type.in(id_DFFSE)) || (ff->type.in(id_DFFP) && !adj_ff->type.in(id_DFFC)) ||
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(ff->type.in(id_DFFC) && !adj_ff->type.in(id_DFFP)) || (ff->type.in(id_DFFPE) && !adj_ff->type.in(id_DFFCE)) ||
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(ff->type.in(id_DFFCE) && !adj_ff->type.in(id_DFFPE)) ||
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(ff->type.in(id_DFFNS) && !adj_ff->type.in(id_DFFNR)) ||
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(ff->type.in(id_DFFNR) && !adj_ff->type.in(id_DFFNS)) ||
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(ff->type.in(id_DFFNSE) && !adj_ff->type.in(id_DFFNRE)) ||
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(ff->type.in(id_DFFNRE) && !adj_ff->type.in(id_DFFNSE)) ||
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(ff->type.in(id_DFFNP) && !adj_ff->type.in(id_DFFNC)) ||
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(ff->type.in(id_DFFNC) && !adj_ff->type.in(id_DFFNP)) ||
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(ff->type.in(id_DFFNPE) && !adj_ff->type.in(id_DFFNCE)) ||
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(ff->type.in(id_DFFNCE) && !adj_ff->type.in(id_DFFNPE)))) {
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return false;
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}
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// CE, LSR and CLK must match
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const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
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if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
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return true;
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}
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//
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return false;
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// CE, LSR and CLK must match
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const auto &adj_ff_data = fast_cell_info.at(adj_ff->flat_index);
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if (adj_ff_data.ff_lsr == ff_data.ff_lsr) {
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return true;
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}
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//
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return false;
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}
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// modify LUTs with constant inputs
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void GowinImpl::mod_lut_inputs(void) {
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for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
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auto net = ctx->nets.find(netname);
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if (net == ctx->nets.end()) {
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continue;
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}
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NetInfo *constnet = net->second.get();
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for (auto user : constnet->users) {
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CellInfo *uc = user.cell;
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if (ctx->verbose)
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log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
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void GowinImpl::mod_lut_inputs(void)
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{
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for (IdString netname : {ctx->id("$PACKER_GND"), ctx->id("$PACKER_VCC")}) {
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auto net = ctx->nets.find(netname);
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if (net == ctx->nets.end()) {
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continue;
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}
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NetInfo *constnet = net->second.get();
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for (auto user : constnet->users) {
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CellInfo *uc = user.cell;
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if (ctx->verbose)
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log_info("%s user %s\n", ctx->nameOf(constnet), ctx->nameOf(uc));
|
||||
|
||||
if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
|
||||
auto it_param = uc->params.find(id_INIT);
|
||||
if (it_param == uc->params.end())
|
||||
log_error("No initialization for lut found.\n");
|
||||
if (is_lut(uc) && (user.port.str(ctx).at(0) == 'I')) {
|
||||
auto it_param = uc->params.find(id_INIT);
|
||||
if (it_param == uc->params.end())
|
||||
log_error("No initialization for lut found.\n");
|
||||
|
||||
int64_t uc_init = it_param->second.intval;
|
||||
int64_t mask = 0;
|
||||
uint8_t amt = 0;
|
||||
int64_t uc_init = it_param->second.intval;
|
||||
int64_t mask = 0;
|
||||
uint8_t amt = 0;
|
||||
|
||||
if (user.port == id_I0) {
|
||||
mask = 0x5555;
|
||||
amt = 1;
|
||||
} else if (user.port == id_I1) {
|
||||
mask = 0x3333;
|
||||
amt = 2;
|
||||
} else if (user.port == id_I2) {
|
||||
mask = 0x0F0F;
|
||||
amt = 4;
|
||||
} else if (user.port == id_I3) {
|
||||
mask = 0x00FF;
|
||||
amt = 8;
|
||||
} else {
|
||||
log_error("Port number invalid.\n");
|
||||
}
|
||||
if (user.port == id_I0) {
|
||||
mask = 0x5555;
|
||||
amt = 1;
|
||||
} else if (user.port == id_I1) {
|
||||
mask = 0x3333;
|
||||
amt = 2;
|
||||
} else if (user.port == id_I2) {
|
||||
mask = 0x0F0F;
|
||||
amt = 4;
|
||||
} else if (user.port == id_I3) {
|
||||
mask = 0x00FF;
|
||||
amt = 8;
|
||||
} else {
|
||||
log_error("Port number invalid.\n");
|
||||
}
|
||||
|
||||
if ((constnet->name == ctx->id("$PACKER_GND"))) {
|
||||
uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
|
||||
} else {
|
||||
uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
|
||||
}
|
||||
if ((constnet->name == ctx->id("$PACKER_GND"))) {
|
||||
uc_init = (uc_init & mask) | ((uc_init & mask) << amt);
|
||||
} else {
|
||||
uc_init = (uc_init & (mask << amt)) | ((uc_init & (mask << amt)) >> amt);
|
||||
}
|
||||
|
||||
size_t uc_init_len = it_param->second.to_string().length();
|
||||
uc_init &= (1LL << uc_init_len) - 1;
|
||||
size_t uc_init_len = it_param->second.to_string().length();
|
||||
uc_init &= (1LL << uc_init_len) - 1;
|
||||
|
||||
if (ctx->verbose)
|
||||
log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
|
||||
uc_init);
|
||||
if (ctx->verbose)
|
||||
log_info("%s lut config modified from 0x%lX to 0x%lX\n", ctx->nameOf(uc), it_param->second.intval,
|
||||
uc_init);
|
||||
|
||||
it_param->second = Property(uc_init, uc_init_len);
|
||||
uc->disconnectPort(user.port);
|
||||
}
|
||||
}
|
||||
}
|
||||
it_param->second = Property(uc_init, uc_init_len);
|
||||
uc->disconnectPort(user.port);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
|
||||
@ -20,7 +20,7 @@ struct GowinImpl : HimbaechelAPI
|
||||
void init(Context *ctx) override;
|
||||
|
||||
void prePlace() override;
|
||||
void pack() override;
|
||||
void pack() override;
|
||||
|
||||
bool isBelLocationValid(BelId bel, bool explain_invalid) const override;
|
||||
|
||||
@ -36,33 +36,26 @@ struct GowinImpl : HimbaechelAPI
|
||||
struct GowinCellInfo
|
||||
{
|
||||
const NetInfo *lut_f = nullptr;
|
||||
const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
|
||||
const NetInfo *ff_d = nullptr, *ff_ce = nullptr, *ff_clk = nullptr, *ff_lsr = nullptr;
|
||||
};
|
||||
std::vector<GowinCellInfo> fast_cell_info;
|
||||
void assign_cell_info();
|
||||
bool slice_valid(int x, int y, int z) const;
|
||||
|
||||
// modify LUTs with constant inputs
|
||||
void mod_lut_inputs(void);
|
||||
// modify LUTs with constant inputs
|
||||
void mod_lut_inputs(void);
|
||||
|
||||
// Return true if a cell is a LUT
|
||||
inline bool type_is_lut(IdString cell_type) const {
|
||||
return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4);
|
||||
}
|
||||
inline bool is_lut(const CellInfo *cell) const {
|
||||
return type_is_lut(cell->type);
|
||||
}
|
||||
// Return true if a cell is a DFF
|
||||
inline bool type_is_dff(IdString cell_type) const {
|
||||
return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE,
|
||||
id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE,
|
||||
id_DFFR, id_DFFRE, id_DFFNR, id_DFFNRE,
|
||||
id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE,
|
||||
id_DFFC, id_DFFCE, id_DFFNC, id_DFFNCE);
|
||||
}
|
||||
inline bool is_dff(const CellInfo *cell) const {
|
||||
return type_is_dff(cell->type);
|
||||
}
|
||||
// Return true if a cell is a LUT
|
||||
inline bool type_is_lut(IdString cell_type) const { return cell_type.in(id_LUT1, id_LUT2, id_LUT3, id_LUT4); }
|
||||
inline bool is_lut(const CellInfo *cell) const { return type_is_lut(cell->type); }
|
||||
// Return true if a cell is a DFF
|
||||
inline bool type_is_dff(IdString cell_type) const
|
||||
{
|
||||
return cell_type.in(id_DFF, id_DFFE, id_DFFN, id_DFFNE, id_DFFS, id_DFFSE, id_DFFNS, id_DFFNSE, id_DFFR,
|
||||
id_DFFRE, id_DFFNR, id_DFFNRE, id_DFFP, id_DFFPE, id_DFFNP, id_DFFNPE, id_DFFC, id_DFFCE,
|
||||
id_DFFNC, id_DFFNCE);
|
||||
}
|
||||
inline bool is_dff(const CellInfo *cell) const { return type_is_dff(cell->type); }
|
||||
};
|
||||
|
||||
struct GowinArch : HimbaechelArch
|
||||
@ -77,4 +70,3 @@ struct GowinArch : HimbaechelArch
|
||||
|
||||
NEXTPNR_NAMESPACE_END
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user