Get rid of old iCE40 id_ Arch members
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
e03ae50e21
commit
f875a37467
@ -92,29 +92,6 @@ Arch::Arch(ArchArgs args) : args(args)
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wire_to_net.resize(chip_info->num_wires);
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pip_to_net.resize(chip_info->num_pips);
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switches_locked.resize(chip_info->num_switches);
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// Initialise regularly used IDStrings for performance
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id_glb_buf_out = id("GLOBAL_BUFFER_OUTPUT");
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id_icestorm_lc = id("ICESTORM_LC");
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id_sb_io = id("SB_IO");
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id_sb_gb = id("SB_GB");
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id_cen = id("CEN");
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id_clk = id("CLK");
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id_sr = id("SR");
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id_i0 = id("I0");
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id_i1 = id("I1");
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id_i2 = id("I2");
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id_i3 = id("I3");
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id_dff_en = id("DFF_ENABLE");
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id_carry_en = id("CARRY_ENABLE");
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id_neg_clk = id("NEG_CLK");
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id_cin = id("CIN");
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id_cout = id("COUT");
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id_o = id("O");
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id_lo = id("LO");
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id_icestorm_ram = id("ICESTORM_RAM");
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id_rclk = id("RCLK");
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id_wclk = id("WCLK");
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}
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// -----------------------------------------------------------------------
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@ -553,7 +530,7 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
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bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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{
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const auto &driver = net_info->driver;
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if (driver.port == id_cout && sink.port == id_cin) {
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if (driver.port == id_COUT && sink.port == id_CIN) {
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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if (driver_loc.y == sink_loc.y)
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@ -795,23 +772,23 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
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IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
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{
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if (cell->type == id_icestorm_lc && cell->lcInfo.dffEnable) {
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if (port != id_lo && port != id_cin && port != id_cout)
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return id_clk;
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} else if (cell->type == id_icestorm_ram) {
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if (cell->type == id_ICESTORM_LC && cell->lcInfo.dffEnable) {
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if (port != id_LO && port != id_CIN && port != id_COUT)
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return id_CLK;
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} else if (cell->type == id_ICESTORM_RAM) {
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if (port.str(this)[0] == 'R')
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return id_rclk;
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return id_RCLK;
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else
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return id_wclk;
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return id_WCLK;
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}
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return IdString();
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}
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bool Arch::isClockPort(const CellInfo *cell, IdString port) const
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{
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if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
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if (cell->type == id_ICESTORM_LC && port == id_CLK)
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return true;
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if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
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if (cell->type == id_ICESTORM_RAM && (port == id_RCLK || port == id_WCLK))
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return true;
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return false;
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}
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@ -820,7 +797,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const
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{
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if (net == nullptr)
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return false;
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return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
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return net->driver.cell != nullptr && net->driver.port == id_GLOBAL_BUFFER_OUTPUT;
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}
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// Assign arch arg info
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@ -849,20 +826,20 @@ void Arch::assignCellInfo(CellInfo *cell)
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{
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cell->belType = cell->type;
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if (cell->type == id_ICESTORM_LC) {
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cell->lcInfo.dffEnable = bool_or_default(cell->params, id_dff_en);
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cell->lcInfo.carryEnable = bool_or_default(cell->params, id_carry_en);
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cell->lcInfo.negClk = bool_or_default(cell->params, id_neg_clk);
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cell->lcInfo.clk = get_net_or_empty(cell, id_clk);
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cell->lcInfo.cen = get_net_or_empty(cell, id_cen);
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cell->lcInfo.sr = get_net_or_empty(cell, id_sr);
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cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
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cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
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cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
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cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
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cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
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cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
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cell->lcInfo.inputCount = 0;
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if (get_net_or_empty(cell, id_i0))
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if (get_net_or_empty(cell, id_I0))
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cell->lcInfo.inputCount++;
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if (get_net_or_empty(cell, id_i1))
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if (get_net_or_empty(cell, id_I1))
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cell->lcInfo.inputCount++;
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if (get_net_or_empty(cell, id_i2))
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if (get_net_or_empty(cell, id_I2))
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cell->lcInfo.inputCount++;
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if (get_net_or_empty(cell, id_i3))
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if (get_net_or_empty(cell, id_I3))
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cell->lcInfo.inputCount++;
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}
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}
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11
ice40/arch.h
11
ice40/arch.h
@ -437,7 +437,7 @@ struct Arch : BaseCtx
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NPNR_ASSERT(bel_to_cell[bel.index] == nullptr);
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bel_to_cell[bel.index] = cell;
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bel_carry[bel.index] = (cell->type == id_icestorm_lc && cell->lcInfo.carryEnable);
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bel_carry[bel.index] = (cell->type == id_ICESTORM_LC && cell->lcInfo.carryEnable);
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cell->bel = bel;
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cell->belStrength = strength;
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refreshUiBel(bel);
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@ -810,15 +810,6 @@ struct Arch : BaseCtx
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void assignArchInfo();
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void assignCellInfo(CellInfo *cell);
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IdString id_glb_buf_out;
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IdString id_icestorm_lc, id_sb_io, id_sb_gb;
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IdString id_cen, id_clk, id_sr;
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IdString id_i0, id_i1, id_i2, id_i3;
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IdString id_dff_en, id_carry_en, id_neg_clk;
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IdString id_cin, id_cout;
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IdString id_o, id_lo;
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IdString id_icestorm_ram, id_rclk, id_wclk;
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// -------------------------------------------------
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BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const
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{
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@ -91,7 +91,7 @@ bool Arch::isBelLocationValid(BelId bel) const
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bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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{
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if (cell->type == id_icestorm_lc) {
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if (cell->type == id_ICESTORM_LC) {
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NPNR_ASSERT(getBelType(bel) == id_ICESTORM_LC);
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std::vector<const CellInfo *> bel_cells;
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@ -105,7 +105,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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bel_cells.push_back(cell);
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return logicCellsCompatible(bel_cells);
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} else if (cell->type == id_sb_io) {
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} else if (cell->type == id_SB_IO) {
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// Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
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// Find shared PLL by looking for driving bel siblings from D_IN_0
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@ -137,9 +137,9 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
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}
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}
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return getBelPackagePin(bel) != "";
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} else if (cell->type == id_sb_gb) {
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NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
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const NetInfo *net = cell->ports.at(id_glb_buf_out).net;
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} else if (cell->type == id_SB_GB) {
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NPNR_ASSERT(cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net != nullptr);
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const NetInfo *net = cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net;
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IdString glb_net = getWireName(getBelPinWire(bel, id_GLOBAL_BUFFER_OUTPUT));
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int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
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if (net->is_reset && net->is_enable)
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@ -57,6 +57,8 @@ slow_timings = None
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with open(args.constids) as f:
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for line in f:
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if line.startswith("//"):
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continue
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line = line.replace("(", " ")
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line = line.replace(")", " ")
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line = line.split()
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@ -1,3 +1,4 @@
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// pin and port names
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X(I0)
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X(I1)
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X(I2)
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@ -413,6 +414,7 @@ X(SLEEP)
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X(STANDBY)
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X(WREN)
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// cell and bel types
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X(ICESTORM_LC)
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X(ICESTORM_RAM)
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X(SB_IO)
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@ -428,3 +430,8 @@ X(IO_I3C)
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X(SB_LEDDA_IP)
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X(SB_RGBA_DRV)
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X(ICESTORM_SPRAM)
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// cell parameters
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X(DFF_ENABLE)
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X(CARRY_ENABLE)
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X(NEG_CLK)
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@ -192,7 +192,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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if (driver.port == id_cout) {
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if (driver.port == id_COUT) {
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if (driver_loc.y == sink_loc.y)
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return 0;
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return 250;
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