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Change how package pin IO sites are selected.

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The first site type that matches is now selected, under the premise that
the early site types are more general.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-02-16 17:25:16 -08:00
parent cc687b3b72
commit f9bd692f75
3 changed files with 52 additions and 16 deletions
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16
fpga_interchange/arch.cc
View File

@ -174,6 +174,22 @@ Arch::Arch(ArchArgs args) : args(args)
definition.states.push_back(IdString(state));
}
}
// Logic BELs (e.g. placable BELs) should always appear first in the
// bel data list.
//
// When iterating over BELs this property is depended on to skip
// non-placable BELs (e.g. routing BELs and site ports).
bool in_logic_bels = true;
for (const BelInfoPOD &bel_info : tile_type.bel_data) {
if (in_logic_bels && bel_info.category != BEL_CATEGORY_LOGIC) {
in_logic_bels = false;
}
if (!in_logic_bels) {
NPNR_ASSERT(bel_info.category != BEL_CATEGORY_LOGIC);
}
}
}
default_tags.resize(max_tag_count);

40
fpga_interchange/arch_pack_io.cc
View File

@ -67,7 +67,7 @@ void Arch::pack_ports()
// set(site_types) for package pins
std::unordered_set<IdString> package_sites;
// Package pin -> (Site type -> BelId)
std::unordered_map<IdString, std::unordered_map<IdString, BelId>> package_pin_bels;
std::unordered_map<IdString, std::vector<std::pair<IdString, BelId>>> package_pin_bels;
for (const PackagePinPOD &package_pin : chip_info->packages[package_index].pins) {
IdString pin(package_pin.package_pin);
IdString bel(package_pin.bel);
@ -94,7 +94,7 @@ void Arch::pack_ports()
BelId bel;
bel.tile = i;
bel.index = j;
package_pin_bels[pin][site_type] = bel;
package_pin_bels[pin].push_back(std::make_pair(site_type, bel));
}
}
}
@ -156,6 +156,10 @@ void Arch::pack_ports()
for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) {
IdString tile_type_name(tile_type.name);
for (const BelInfoPOD &bel_info : tile_type.bel_data) {
if (bel_info.category != BEL_CATEGORY_LOGIC) {
break;
}
for (IdString cell_type : cell_types_in_io_group) {
size_t cell_type_index = get_cell_type_index(cell_type);
if (bel_info.category == BEL_CATEGORY_LOGIC && bel_info.pin_map[cell_type_index] != -1) {
@ -175,6 +179,13 @@ void Arch::pack_ports()
log_error("Port '%s' has no possible site types!\n", port_name.c_str(getCtx()));
}
if (getCtx()->verbose) {
log_info("Possible site types for port %s\n", port_name.c_str(getCtx()));
for (IdString site_type : possible_site_types) {
log_info(" - %s\n", site_type.c_str(getCtx()));
}
}
auto iter = port_cell->attrs.find(id("PACKAGE_PIN"));
if (iter == port_cell->attrs.end()) {
// FIXME: Relax this constraint
@ -188,28 +199,37 @@ void Arch::pack_ports()
log_error("Package pin '%s' not found in part %s\n", package_pin_id.c_str(getCtx()), get_part().c_str());
}
NPNR_ASSERT(pin_iter != package_pin_bels.end());
const auto &site_type_to_bel = pin_iter->second;
// Select the first BEL from package_bel_pins that is a legal site
// type.
//
// This is likely the most generic (versus specialized) site type.
BelId package_bel;
for (IdString site_type : possible_site_types) {
auto site_iter = site_type_to_bel.find(site_type);
if (site_iter != site_type_to_bel.end()) {
for (auto site_type_and_bel : pin_iter->second) {
IdString legal_site_type = site_type_and_bel.first;
BelId bel = site_type_and_bel.second;
if (possible_site_types.count(legal_site_type)) {
// FIXME: Need to handle case where a port can be in multiple
// modes, but only one of the modes works.
//
// NPNR_ASSERT(package_bel == BelId());
package_bel = site_iter->second;
package_bel = bel;
break;
}
}
if (package_bel == BelId()) {
log_info("Failed to find BEL for package pin '%s' in any possible site types:\n", package_pin_id.c_str(getCtx()));
log_info("Failed to find BEL for package pin '%s' in any possible site types:\n",
package_pin_id.c_str(getCtx()));
for (IdString site_type : possible_site_types) {
log_info(" - %s\n", site_type.c_str(getCtx()));
}
log_error("Failed to find BEL for package pin '%s'\n", package_pin_id.c_str(getCtx()));
}
if (getCtx()->verbose) {
log_info("Binding port %s to BEL %s\n", port_name.c_str(getCtx()), getCtx()->nameOfBel(package_bel));
}
std::unordered_set<CellInfo *> placed_cells;
bindBel(package_bel, port_cell, STRENGTH_FIXED);
placed_cells.emplace(port_cell);

2
fpga_interchange/main.cc
View File

@ -20,8 +20,8 @@
#ifdef MAIN_EXECUTABLE
#include <fstream>
#include <chrono>
#include <fstream>
#include "command.h"
#include "design_utils.h"