From fae7994bc34b302dbd35c0793a9ce9f81234dbc1 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Tue, 24 Jul 2018 01:38:20 +0100 Subject: [PATCH] clang-format --- common/router1.cc | 1 - ice40/bitstream.cc | 35 ++++++++++-------- ice40/cells.h | 1 - ice40/pack.cc | 90 +++++++++++++++++++++++----------------------- 4 files changed, 67 insertions(+), 60 deletions(-) diff --git a/common/router1.cc b/common/router1.cc index 21c54e4c..fbf3c467 100644 --- a/common/router1.cc +++ b/common/router1.cc @@ -210,7 +210,6 @@ struct Router else overtimeRevisitCnt++; } - QueuedWire next_qw; next_qw.wire = next_wire; diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index c388fe2b..1d799307 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -88,7 +88,9 @@ void set_config(const TileInfoPOD &ti, std::vector> &tile_cf // Set an IE_{EN,REN} logical bit in a tile config. Logical means enabled. // On {HX,LP}1K devices these bits are active low, so we need to inver them. -void set_ie_bit_logical(const Context *ctx, const TileInfoPOD &ti, std::vector> &tile_cfg, const std::string &name, bool value) { +void set_ie_bit_logical(const Context *ctx, const TileInfoPOD &ti, std::vector> &tile_cfg, + const std::string &name, bool value) +{ if (ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K) { set_config(ti, tile_cfg, name, !value); } else { @@ -320,7 +322,7 @@ void write_asc(const Context *ctx, std::ostream &out) } else if (cell.second->type == ctx->id("SB_IO")) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; - sb_io_used_by_user.insert(Loc(x,y,z)); + sb_io_used_by_user.insert(Loc(x, y, z)); const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE")); bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER")); @@ -424,14 +426,20 @@ void write_asc(const Context *ctx, std::ostream &out) {"B_SIGNED", 1}}; configure_extra_cell(config, ctx, cell.second.get(), mac16_params, false, std::string("IpConfig.")); } else if (cell.second->type == ctx->id("ICESTORM_PLL")) { - const std::vector> pll_params = { - {"DELAY_ADJMODE_FB", 1}, {"DELAY_ADJMODE_REL", 1}, - {"DIVF", 7}, {"DIVQ", 3}, {"DIVR", 4}, - {"FDA_FEEDBACK", 4}, {"FDA_RELATIVE", 4}, - {"FEEDBACK_PATH", 3}, {"FILTER_RANGE", 3}, - {"PLLOUT_SELECT_A", 2}, {"PLLOUT_SELECT_B", 2}, - {"PLLTYPE", 3}, {"SHIFTREG_DIV_MODE", 1}, {"TEST_MODE", 1} - }; + const std::vector> pll_params = {{"DELAY_ADJMODE_FB", 1}, + {"DELAY_ADJMODE_REL", 1}, + {"DIVF", 7}, + {"DIVQ", 3}, + {"DIVR", 4}, + {"FDA_FEEDBACK", 4}, + {"FDA_RELATIVE", 4}, + {"FEEDBACK_PATH", 3}, + {"FILTER_RANGE", 3}, + {"PLLOUT_SELECT_A", 2}, + {"PLLOUT_SELECT_B", 2}, + {"PLLTYPE", 3}, + {"SHIFTREG_DIV_MODE", 1}, + {"TEST_MODE", 1}}; configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL.")); // Configure the SB_IOs that the clock outputs are going through. @@ -458,8 +466,7 @@ void write_asc(const Context *ctx, std::ostream &out) // Check that this SB_IO is either unused or just used as an output. auto io_loc = Loc(io_beli.x, io_beli.y, io_beli.z); if (sb_io_used_by_user.count(io_loc)) { - log_error("SB_IO '%s' already in use, cannot route PLL through\n", - ctx->getBelName(bel).c_str(ctx)); + log_error("SB_IO '%s' already in use, cannot route PLL through\n", ctx->getBelName(bel).c_str(ctx)); } sb_io_used_by_pll.insert(Loc(io_beli.x, io_beli.y, io_beli.z)); @@ -476,8 +483,8 @@ void write_asc(const Context *ctx, std::ostream &out) set_ie_bit_logical(ctx, ti, config.at(iey).at(iex), "IoCtrl.IE_" + std::to_string(iez), true); set_ie_bit_logical(ctx, ti, config.at(iey).at(iex), "IoCtrl.REN_" + std::to_string(iez), false); // PINTYPE[0] passes the PLL through to the fabric. - set_config(ti, config.at(io_beli.y).at(io_beli.x), "IOB_" + std::to_string(io_beli.z) + ".PINTYPE_0", true); - + set_config(ti, config.at(io_beli.y).at(io_beli.x), "IOB_" + std::to_string(io_beli.z) + ".PINTYPE_0", + true); } } else { diff --git a/ice40/cells.h b/ice40/cells.h index 4bc50e8a..16135448 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -84,7 +84,6 @@ inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell) cell->type == ctx->id("SB_PLL40_2F_PAD"); } - uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell); // Convert a SB_LUT primitive to (part of) an ICESTORM_LC, swapping ports diff --git a/ice40/pack.cc b/ice40/pack.cc index 14abc1d0..8552e381 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -541,51 +541,50 @@ static void promote_globals(Context *ctx) // and either all users or only non_LUT users. static std::unique_ptr spliceLUT(Context *ctx, CellInfo *ci, IdString portId, bool onlyNonLUTs) { - auto port = ci->ports[portId]; + auto port = ci->ports[portId]; - NPNR_ASSERT(port.net != nullptr); + NPNR_ASSERT(port.net != nullptr); + // Create pass-through LUT. + std::unique_ptr pt = + create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "$nextpnr_ice40_pack_pll_lc"); + pt->params[ctx->id("LUT_INIT")] = "255"; // output is always I3 - // Create pass-through LUT. - std::unique_ptr pt = - create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "$nextpnr_ice40_pack_pll_lc"); - pt->params[ctx->id("LUT_INIT")] = "255"; // output is always I3 + // Create LUT output net. + std::unique_ptr out_net = std::unique_ptr(new NetInfo); + out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_ice40_pack_pll_net"); + out_net->driver.cell = pt.get(); + out_net->driver.port = ctx->id("O"); + pt->ports.at(ctx->id("O")).net = out_net.get(); - // Create LUT output net. - std::unique_ptr out_net = std::unique_ptr(new NetInfo); - out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_ice40_pack_pll_net"); - out_net->driver.cell = pt.get(); - out_net->driver.port = ctx->id("O"); - pt->ports.at(ctx->id("O")).net = out_net.get(); + // New users of the original cell's port + std::vector new_users; + for (const auto &user : port.net->users) { + if (onlyNonLUTs && user.cell->type == ctx->id("ICESTORM_LC")) { + new_users.push_back(user); + continue; + } + // Rewrite pointer into net in user. + user.cell->ports[user.port].net = out_net.get(); + // Add user to net. + PortRef pr; + pr.cell = user.cell; + pr.port = user.port; + out_net->users.push_back(pr); + } - // New users of the original cell's port - std::vector new_users; - for (const auto &user : port.net->users) { - if (onlyNonLUTs && user.cell->type == ctx->id("ICESTORM_LC")) { - new_users.push_back(user); - continue; - } - // Rewrite pointer into net in user. - user.cell->ports[user.port].net = out_net.get(); - // Add user to net. - PortRef pr; - pr.cell = user.cell; - pr.port = user.port; - out_net->users.push_back(pr); - } + // Add LUT to new users. + PortRef pr; + pr.cell = pt.get(); + pr.port = ctx->id("I3"); + new_users.push_back(pr); + pt->ports.at(ctx->id("I3")).net = port.net; - // Add LUT to new users. - PortRef pr; - pr.cell = pt.get(); - pr.port = ctx->id("I3"); - new_users.push_back(pr); - pt->ports.at(ctx->id("I3")).net = port.net; + // Replace users of the original net. + port.net->users = new_users; - // Replace users of the original net. - port.net->users = new_users; - - ctx->nets[out_net->name] = std::move(out_net); - return pt; + ctx->nets[out_net->name] = std::move(out_net); + return pt; } // Pack special functions @@ -660,10 +659,13 @@ static void pack_special(Context *ctx) packed->params[param.first] = param.second; auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")]; - packed->params[ctx->id("FEEDBACK_PATH")] = feedback_path == "DELAY" ? "0" : - feedback_path == "SIMPLE" ? "1" : - feedback_path == "PHASE_AND_DELAY" ? "2" : - feedback_path == "EXTERNAL" ? "6" : feedback_path; + packed->params[ctx->id("FEEDBACK_PATH")] = + feedback_path == "DELAY" + ? "0" + : feedback_path == "SIMPLE" ? "1" + : feedback_path == "PHASE_AND_DELAY" + ? "2" + : feedback_path == "EXTERNAL" ? "6" : feedback_path; packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci)); for (auto port : ci->ports) { @@ -687,7 +689,7 @@ static void pack_special(Context *ctx) BelId pll_bel; bool constrained = false; if (packed->attrs.find(ctx->id("BEL")) == packed->attrs.end()) { - //FIXME replace by getBelsByType when implemented + // FIXME replace by getBelsByType when implemented for (auto bel : ctx->getBels()) { if (ctx->getBelType(bel) != TYPE_ICESTORM_PLL) continue; @@ -759,7 +761,7 @@ static void pack_special(Context *ctx) // target of another constraint. NPNR_ASSERT(z < 8); auto target_bel = ctx->getBelByLocation(Loc(x, y, z++)); - auto target_bel_name = ctx->getBelName(target_bel).str(ctx); + auto target_bel_name = ctx->getBelName(target_bel).str(ctx); user.cell->attrs[ctx->id("BEL")] = target_bel_name; log_info(" constrained '%s' to %s\n", user.cell->name.c_str(ctx), target_bel_name.c_str()); }