timing: Fix timing analysis when no paths found (e.g. ecp5 with no cell timing info yet)
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -176,35 +176,40 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
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PortRefList crit_path;
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delay_t min_slack = walk_paths(ctx, false, &crit_path);
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if (print_path) {
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delay_t total = 0;
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log_break();
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log_info("Critical path report:\n");
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log_info("curr total\n");
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayInfo comb_delay;
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ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
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total += comb_delay.maxDelay();
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log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
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driver.port.c_str(ctx));
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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total += net_delay;
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auto driver_loc = ctx->getBelLocation(driver_cell->bel);
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auto sink_loc = ctx->getBelLocation(sink_cell->bel);
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log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
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sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
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last_port = sink->port;
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if (crit_path.empty()) {
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log_info("Design contains no timing paths\n");
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} else {
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delay_t total = 0;
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log_break();
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log_info("Critical path report:\n");
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log_info("curr total\n");
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
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for (auto sink : crit_path) {
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auto sink_cell = sink->cell;
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auto &port = sink_cell->ports.at(sink->port);
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auto net = port.net;
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auto &driver = net->driver;
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auto driver_cell = driver.cell;
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DelayInfo comb_delay;
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ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
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total += comb_delay.maxDelay();
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log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
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driver.port.c_str(ctx));
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auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
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total += net_delay;
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auto driver_loc = ctx->getBelLocation(driver_cell->bel);
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auto sink_loc = ctx->getBelLocation(sink_cell->bel);
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log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
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sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
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log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
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last_port = sink->port;
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}
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log_break();
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}
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log_break();
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}
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if (print_fmax)
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log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
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