timing: Fix timing analysis when no paths found (e.g. ecp5 with no cell timing info yet)
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -176,10 +176,14 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
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PortRefList crit_path;
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PortRefList crit_path;
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delay_t min_slack = walk_paths(ctx, false, &crit_path);
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delay_t min_slack = walk_paths(ctx, false, &crit_path);
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if (print_path) {
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if (print_path) {
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if (crit_path.empty()) {
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log_info("Design contains no timing paths\n");
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} else {
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delay_t total = 0;
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delay_t total = 0;
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log_break();
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log_break();
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log_info("Critical path report:\n");
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log_info("Critical path report:\n");
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log_info("curr total\n");
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log_info("curr total\n");
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auto &front = crit_path.front();
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auto &front = crit_path.front();
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_port = front->cell->ports.at(front->port);
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auto &front_driver = front_port.net->driver;
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auto &front_driver = front_port.net->driver;
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@ -206,6 +210,7 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
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}
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}
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log_break();
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log_break();
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}
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}
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}
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if (print_fmax)
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if (print_fmax)
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log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
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log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
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return min_slack;
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return min_slack;
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