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timing: Fix timing analysis when no paths found (e.g. ecp5 with no cell timing info yet)

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-08-01 11:23:11 +02:00
parent fa4fb52665
commit faf309c1fe
1 changed files with 33 additions and 28 deletions
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61
common/timing.cc
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@ -176,35 +176,40 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
PortRefList crit_path; PortRefList crit_path;
delay_t min_slack = walk_paths(ctx, false, &crit_path); delay_t min_slack = walk_paths(ctx, false, &crit_path);
if (print_path) { if (print_path) {
delay_t total = 0; if (crit_path.empty()) {
log_break(); log_info("Design contains no timing paths\n");
log_info("Critical path report:\n"); } else {
log_info("curr total\n"); delay_t total = 0;
auto &front = crit_path.front(); log_break();
auto &front_port = front->cell->ports.at(front->port); log_info("Critical path report:\n");
auto &front_driver = front_port.net->driver; log_info("curr total\n");
auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
for (auto sink : crit_path) { auto &front = crit_path.front();
auto sink_cell = sink->cell; auto &front_port = front->cell->ports.at(front->port);
auto &port = sink_cell->ports.at(sink->port); auto &front_driver = front_port.net->driver;
auto net = port.net; auto last_port = ctx->getPortClock(front_driver.cell, front_driver.port);
auto &driver = net->driver; for (auto sink : crit_path) {
auto driver_cell = driver.cell; auto sink_cell = sink->cell;
DelayInfo comb_delay; auto &port = sink_cell->ports.at(sink->port);
ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay); auto net = port.net;
total += comb_delay.maxDelay(); auto &driver = net->driver;
log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx), auto driver_cell = driver.cell;
driver.port.c_str(ctx)); DelayInfo comb_delay;
auto net_delay = ctx->getNetinfoRouteDelay(net, *sink); ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
total += net_delay; total += comb_delay.maxDelay();
auto driver_loc = ctx->getBelLocation(driver_cell->bel); log_info("%4d %4d Source %s.%s\n", comb_delay.maxDelay(), total, driver_cell->name.c_str(ctx),
auto sink_loc = ctx->getBelLocation(sink_cell->bel); driver.port.c_str(ctx));
log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx), auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y); total += net_delay;
log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx)); auto driver_loc = ctx->getBelLocation(driver_cell->bel);
last_port = sink->port; auto sink_loc = ctx->getBelLocation(sink_cell->bel);
log_info("%4d %4d Net %s budget %d (%d,%d) -> (%d,%d)\n", net_delay, total, net->name.c_str(ctx),
sink->budget, driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y);
log_info(" Sink %s.%s\n", sink_cell->name.c_str(ctx), sink->port.c_str(ctx));
last_port = sink->port;
}
log_break();
} }
log_break();
} }
if (print_fmax) if (print_fmax)
log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack)); log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));