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timing: Fix timing analysis when no paths found (e.g. ecp5 with no cell timing info yet)

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-08-01 11:23:11 +02:00
parent fa4fb52665
commit faf309c1fe
1 changed files with 33 additions and 28 deletions
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5
common/timing.cc
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@ -176,10 +176,14 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
PortRefList crit_path;
delay_t min_slack = walk_paths(ctx, false, &crit_path);
if (print_path) {
if (crit_path.empty()) {
log_info("Design contains no timing paths\n");
} else {
delay_t total = 0;
log_break();
log_info("Critical path report:\n");
log_info("curr total\n");
auto &front = crit_path.front();
auto &front_port = front->cell->ports.at(front->port);
auto &front_driver = front_port.net->driver;
@ -206,6 +210,7 @@ delay_t timing_analysis(Context *ctx, bool print_fmax, bool print_path)
}
log_break();
}
}
if (print_fmax)
log_info("estimated Fmax = %.2f MHz\n", 1e6 / (default_slack - min_slack));
return min_slack;